From e4a3b44e8e24bfffbda46989e19316106026eba7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 15 May 2026 12:34:54 +0200 Subject: [PATCH] Fixed not intentional log_signal removal --- backends/aiger2/aiger.cc | 2 +- passes/techmap/bufnorm.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c0ab8a65c..6d8ac8a24 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1048,7 +1048,7 @@ struct XAigerWriter : AigerWriter { } else if (!is_input && !inputs) { for (auto &bit : conn.second) { if (!bit.wire || (bit.wire->port_input && !bit.wire->port_output)) - log_error("Bad connection %s/%s ~ %s\n", box, conn.first.unescape(), conn.second); + log_error("Bad connection %s/%s ~ %s\n", box, conn.first.unescape(), log_signal(conn.second)); ensure_pi(bit, cursor); diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc index 9e6ca2e30..c27f2740d 100644 --- a/passes/techmap/bufnorm.cc +++ b/passes/techmap/bufnorm.cc @@ -502,7 +502,7 @@ struct BufnormPass : public Pass { if (conn.second != newsig) { log(" fixing input signal on cell %s port %s: %s\n", - cell, conn.first.unescape(), newsig); + cell, conn.first.unescape(), log_signal(newsig)); cell->setPort(conn.first, newsig); count_updated_cellports++; }