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signorm: skip const when fixing fanout

This commit is contained in:
Emil J. Tywoniak 2026-03-17 11:28:10 +01:00
parent 74610ae0ee
commit e2f9a31b8d

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@ -143,7 +143,8 @@ struct RTLIL::SigNormIndex
continue;
int i = 0;
for (auto bit : sig)
fanout[bit].insert(PortBit(cell, port, i++));
if (bit.is_wire())
fanout[bit].insert(PortBit(cell, port, i++));
}
}
}
@ -964,6 +965,8 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
@ -1091,6 +1094,8 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
auto &fanout = module->sig_norm_index->fanout;
int counter = 0;
for (auto bit : conn_it->second) {
if (!bit.is_wire())
continue;
int i = counter++;
auto found = fanout.find(bit);
log_assert(found != fanout.end());
@ -1112,7 +1117,8 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
auto &fanout = module->sig_norm_index->fanout;
int i = 0;
for (auto bit : signal)
fanout[bit].insert(PortBit(this, portname, i++));
if (bit.is_wire())
fanout[bit].insert(PortBit(this, portname, i++));
} else if (GetSize(signal)) {
Wire *w = signal.as_wire();
log_assert(w->driverCell_ == nullptr);