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Verific UPF eval working
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parent
9e2a89070d
commit
e2659247fc
3 changed files with 18 additions and 3 deletions
10
Makefile
10
Makefile
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@ -19,12 +19,14 @@ ENABLE_GHDL := 0
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ENABLE_SLANG := 0
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ENABLE_VERIFIC := 1
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ENABLE_VERIFIC_SYSTEMVERILOG := 1
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ENABLE_VERIFIC_GHDL := 0
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ENABLE_VERIFIC_VHDL := 0
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ENABLE_VERIFIC_HIER_TREE := 1
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ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
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ENABLE_VERIFIC_EDIF := 0
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ENABLE_VERIFIC_LIBERTY := 0
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ENABLE_VERIFIC_UPF := 0
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ENABLE_VERIFIC_UPF := 1
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ENABLE_COVER := 1
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ENABLE_LIBYOSYS := 0
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ENABLE_ZLIB := 1
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@ -522,6 +524,9 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
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VERIFIC_COMPONENTS += verilog
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endif
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endif
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ifeq ($(ENABLE_VERIFIC_GHDL),1)
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CXXFLAGS += -DVERIFIC_GHDL_SUPPORT
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endif
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ifeq ($(ENABLE_VERIFIC_VHDL),1)
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VERIFIC_COMPONENTS += vhdl
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CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
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@ -543,6 +548,9 @@ VERIFIC_COMPONENTS += hdl_file_sort verilog_nl
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VERIFIC_COMPONENTS += commands upf
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CXXFLAGS += -DVERIFIC_UPF_SUPPORT
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endif
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ifeq ($(ENABLE_VERIFIC_SILIMATE_EXTENSIONS),1)
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CXXFLAGS += -DSILIMATE_VERIFIC_EXTENSIONS
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endif
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ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
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VERIFIC_COMPONENTS += extensions
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CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
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