From e2659247fc0ec87db100e4d159d116d854ae139b Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 17 Oct 2024 04:40:38 -0700
Subject: [PATCH] Verific UPF eval working

---
 Makefile                     | 10 +++++++++-
 frontends/verific/verific.cc |  9 ++++++++-
 verific                      |  2 +-
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 6241e472f..1efab0d26 100644
--- a/Makefile
+++ b/Makefile
@@ -19,12 +19,14 @@ ENABLE_GHDL := 0
 ENABLE_SLANG := 0
 ENABLE_VERIFIC := 1
 ENABLE_VERIFIC_SYSTEMVERILOG := 1
+ENABLE_VERIFIC_GHDL := 0
 ENABLE_VERIFIC_VHDL := 0
 ENABLE_VERIFIC_HIER_TREE := 1
+ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
 ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-ENABLE_VERIFIC_UPF := 0
+ENABLE_VERIFIC_UPF := 1
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -522,6 +524,9 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
 VERIFIC_COMPONENTS += verilog
 endif
 endif
+ifeq ($(ENABLE_VERIFIC_GHDL),1)
+CXXFLAGS += -DVERIFIC_GHDL_SUPPORT
+endif
 ifeq ($(ENABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
@@ -543,6 +548,9 @@ VERIFIC_COMPONENTS += hdl_file_sort verilog_nl
 VERIFIC_COMPONENTS += commands upf
 CXXFLAGS += -DVERIFIC_UPF_SUPPORT
 endif
+ifeq ($(ENABLE_VERIFIC_SILIMATE_EXTENSIONS),1)
+CXXFLAGS += -DSILIMATE_VERIFIC_EXTENSIONS
+endif
 ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
 VERIFIC_COMPONENTS += extensions
 CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6a318b1e3..8a80e0d0d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -3658,8 +3658,10 @@ struct VerificPass : public Pass {
 			veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG);
 			veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG);
 			veri_file::AddFileExtMode(".inc", veri_file::SYSTEM_VERILOG);
+#ifdef VERIFIC_GHDL_SUPPORT
 			veri_file::AddFileExtMode(".vhd", veri_file::VHDL);
 			veri_file::AddFileExtMode(".vhdl", veri_file::VHDL);
+#endif
 			goto check_error;
 		}
 
@@ -3677,8 +3679,11 @@ struct VerificPass : public Pass {
 			bool is_formal = false;
 			const char* filename = nullptr;
 
+#ifndef SILIMATE_VERIFIC_EXTENSIONS
 			Verific::veri_file::f_file_flags flags = (args[argidx] == "-F") ? veri_file::F_FILE_CAPITAL : (args[argidx] == "-FF" ? veri_file::F_FILE_CAPITAL_NESTED : veri_file::F_FILE_NONE);
-
+#else
+			Verific::veri_file::f_file_flags flags = (args[argidx] == "-F") ? veri_file::F_FILE_CAPITAL : veri_file::F_FILE_NONE;
+#endif
 			for (argidx++; argidx < GetSize(args); argidx++) {
 				if (args[argidx] == "-vlog95") {
 					verilog_mode = veri_file::VERILOG_95;
@@ -3723,6 +3728,7 @@ struct VerificPass : public Pass {
 			*/
 
 			// SILIMATE: VHDL processing using GHDL
+#ifdef VERIFIC_GHDL_SUPPORT
 			int i;
 			FOREACH_ARRAY_ITEM(file_names, i, filename) {
 				// Convert filename to std::string
@@ -3767,6 +3773,7 @@ struct VerificPass : public Pass {
 				// Add file
 				file_names->Insert(i, Strings::save(outfile.c_str()));
 			}
+#endif
 
 			if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
 				verific_error_msg.clear();
diff --git a/verific b/verific
index fbd43f10f..e4d48d931 160000
--- a/verific
+++ b/verific
@@ -1 +1 @@
-Subproject commit fbd43f10f5c6e615b6a73395a11a010434cbb4f5
+Subproject commit e4d48d93116d234d8a54e3e0c2293bb9b15dbd2c