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Remove .c_str() calls from log()/log_error()

Browse source 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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4
backends/aiger/aiger.cc
View file

@ -1040,7 +1040,7 @@ struct AigerBackend : public Backend {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
writer.write_map(mapf, verbose_map, no_startoffset);
}
@ -1051,7 +1051,7 @@ struct AigerBackend : public Backend {
PrettyJson json;
if (!json.write_to_file(yw_map_filename))
log_error("Can't open file `%s' for writing: %s\n", yw_map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", yw_map_filename, strerror(errno));
writer.write_ywmap(json);
}
}

2
backends/aiger/xaiger.cc
View file

@ -788,7 +788,7 @@ struct XAigerBackend : public Backend {
std::ofstream mapf;
mapf.open(map_filename.c_str(), std::ofstream::trunc);
if (mapf.fail())
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno));
writer.write_map(mapf);
}
}

2
backends/blif/blif.cc
View file

@ -674,7 +674,7 @@ struct BlifBackend : public Backend {
}
if (!top_module_name.empty())
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
log_error("Can't find top module `%s'!\n", top_module_name);
for (auto module : mod_list)
BlifDumper::dump(*f, module, design, config);

4
backends/btor/btor.cc
View file

@ -246,7 +246,7 @@ struct BtorWorker
string cell_list;
for (auto c : cell_recursion_guard)
cell_list += stringf("\n %s", log_id(c));
log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str());
log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list);
}
cell_recursion_guard.insert(cell);
@ -1489,7 +1489,7 @@ struct BtorWorker
std::ofstream f;
f.open(info_filename.c_str(), std::ofstream::trunc);
if (f.fail())
log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", info_filename, strerror(errno));
for (auto &it : info_lines)
f << it;
f.close();

2
backends/edif/edif.cc
View file

@ -519,7 +519,7 @@ struct EdifBackend : public Backend {
continue;
} else {
for (auto &ref : it.second)
log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str());
log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first);
log_abort();
}
}

6
backends/firrtl/firrtl.cc
View file

@ -347,7 +347,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
auto modInstance = design->module(cell->type);
// Ensure that we actually have a module instance
if (modInstance == nullptr) {
log_error("Unknown cell type %s\n", cell->type.c_str());
log_error("Unknown cell type %s\n", cell->type);
return;
}
@ -505,14 +505,14 @@ struct FirrtlWorker
sinkExpr = firstName;
break;
default:
log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type, log_signal(it->second), dir);
break;
}
// Check for subfield assignment.
std::string bitsString = "bits(";
if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) {
if (sinkSig == nullptr)
log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
log_error("Unknown subfield %s.%s\n", cell_type, sinkExpr);
// Don't generate the assignment here.
// Add the source and sink to the "reverse_wire_map" and we'll output the assignment
// as part of the coalesced subfield assignments for this wire.

2
backends/functional/cxx.cc
View file

@ -268,7 +268,7 @@ struct FunctionalCxxBackend : public Backend
extra_args(f, filename, args, argidx, design);
for (auto module : design->selected_modules()) {
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
printCxx(*f, filename, module);
}
}

2
backends/functional/smtlib.cc
View file

@ -285,7 +285,7 @@ struct FunctionalSmtBackend : public Backend {
extra_args(f, filename, args, argidx, design);
for (auto module : design->selected_modules()) {
log("Processing module `%s`.\n", module->name.c_str());
log("Processing module `%s`.\n", module->name);
SmtModule smt(module);
smt.write(*f);
}

2
backends/functional/smtlib_rosette.cc
View file

@ -307,7 +307,7 @@ struct FunctionalSmtrBackend : public Backend {
}
for (auto module : design->selected_modules()) {
log("Processing module `%s`.\n", module->name.c_str());
log("Processing module `%s`.\n", module->name);
SmtrModule smtr(module);
smtr.write(*f);
}

2
backends/functional/test_generic.cc
View file

@ -143,7 +143,7 @@ struct FunctionalTestGeneric : public Pass
*/
for (auto module : design->selected_modules()) {
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
auto fir = Functional::IR::from_module(module);
for(auto node : fir)
std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n";

4
backends/intersynth/intersynth.cc
View file

@ -100,13 +100,13 @@ struct IntersynthBackend : public Backend {
}
extra_args(f, filename, args, argidx);
log("Output filename: %s\n", filename.c_str());
log("Output filename: %s\n", filename);
for (auto filename : libfiles) {
std::ifstream f;
f.open(filename.c_str());
if (f.fail())
log_error("Can't open lib file `%s'.\n", filename.c_str());
log_error("Can't open lib file `%s'.\n", filename);
RTLIL::Design *lib = new RTLIL::Design;
Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
libs.push_back(lib);

4
backends/jny/jny.cc
View file

@ -553,7 +553,7 @@ struct JnyPass : public Pass {
ff->open(filename.c_str(), std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
invk << filename;
@ -568,7 +568,7 @@ struct JnyPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}

4
backends/json/json.cc
View file

@ -701,7 +701,7 @@ struct JsonPass : public Pass {
ff->open(filename.c_str(), std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
} else {
@ -714,7 +714,7 @@ struct JsonPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}
} JsonPass;

6
backends/rtlil/rtlil_backend.cc
View file

@ -458,7 +458,7 @@ struct RTLILBackend : public Backend {
design->sort();
log("Output filename: %s\n", filename.c_str());
log("Output filename: %s\n", filename);
*f << stringf("# Generated by %s\n", yosys_maybe_version());
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
@ -531,7 +531,7 @@ struct DumpPass : public Pass {
ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc);
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno));
}
f = ff;
} else {
@ -543,7 +543,7 @@ struct DumpPass : public Pass {
if (!empty) {
delete f;
} else {
log("%s", buf.str().c_str());
log("%s", buf.str());
}
}
} DumpPass;

14
backends/simplec/simplec.cc
View file

@ -504,7 +504,7 @@ struct SimplecWorker
while (work->dirty)
{
if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty()))
log(" In %s:\n", work->log_prefix.c_str());
log(" In %s:\n", work->log_prefix);
while (!work->dirty_bits.empty() || !work->dirty_cells.empty())
{
@ -517,7 +517,7 @@ struct SimplecWorker
if (chunk.wire == nullptr)
continue;
if (verbose)
log(" Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
log(" Propagating %s.%s[%d:%d].\n", work->log_prefix, log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
funct_declarations.push_back(stringf(" // Updated signal in %s: %s", work->log_prefix, log_signal(chunk)));
}
@ -539,7 +539,7 @@ struct SimplecWorker
work->parent->set_dirty(parent_bit);
if (verbose)
log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset,
work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset);
}
@ -556,11 +556,11 @@ struct SimplecWorker
child->set_dirty(child_bit);
if (verbose)
log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset,
work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset);
} else {
if (verbose)
log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)),
log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix, log_id(std::get<0>(port)),
work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
work->set_dirty(std::get<0>(port));
}
@ -579,7 +579,7 @@ struct SimplecWorker
string hiername = work->log_prefix + "." + log_id(cell);
if (verbose)
log(" Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells));
log(" Evaluating %s (%s, best of %d).\n", hiername, log_id(cell->type), GetSize(work->dirty_cells));
if (activated_cells.count(hiername))
reactivated_cells.insert(hiername);
@ -630,7 +630,7 @@ struct SimplecWorker
void make_func(HierDirtyFlags *work, const string &func_name, const vector<string> &preamble)
{
log("Generating function %s():\n", func_name.c_str());
log("Generating function %s():\n", func_name);
activated_cells.clear();
reactivated_cells.clear();

8
backends/smt2/smt2.cc
View file

@ -130,7 +130,7 @@ struct Smt2Worker
for (auto &mem : memories)
{
if (is_smtlib2_module)
log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid.c_str());
log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid);
mem.narrow();
mem_dict[mem.memid] = &mem;
@ -620,11 +620,11 @@ struct Smt2Worker
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr));
if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str().c_str());
log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str());
}
else if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::minimize)){
decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str().c_str());
log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str());
}
bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst));
@ -1776,7 +1776,7 @@ struct Smt2Backend : public Backend {
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
template_f.open(args[++argidx]);
if (template_f.fail())
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
log_error("Can't open template file `%s'.\n", args[argidx]);
continue;
}
if (args[argidx] == "-bv" || args[argidx] == "-mem") {

4
backends/smv/smv.cc
View file

@ -756,7 +756,7 @@ struct SmvBackend : public Backend {
if (args[argidx] == "-tpl" && argidx+1 < args.size()) {
template_f.open(args[++argidx]);
if (template_f.fail())
log_error("Can't open template file `%s'.\n", args[argidx].c_str());
log_error("Can't open template file `%s'.\n", args[argidx]);
continue;
}
if (args[argidx] == "-verbose") {
@ -795,7 +795,7 @@ struct SmvBackend : public Backend {
modules.erase(module);
if (module == nullptr)
log_error("Module '%s' not found.\n", stmt[1].c_str());
log_error("Module '%s' not found.\n", stmt[1]);
*f << stringf("-- SMV description generated by %s\n", yosys_maybe_version());

2
backends/spice/spice.cc
View file

@ -258,7 +258,7 @@ struct SpiceBackend : public Backend {
if (!top_module_name.empty()) {
if (top_module == NULL)
log_error("Can't find top module `%s'!\n", top_module_name.c_str());
log_error("Can't find top module `%s'!\n", top_module_name);
print_spice_module(*f, top_module, design, neg, pos, buf, ncpf, big_endian, use_inames);
*f << stringf("\n");
}

6
backends/verilog/verilog_backend.cc
View file

@ -153,7 +153,7 @@ void reset_auto_counter(RTLIL::Module *module)
if (verbose)
for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it)
log(" renaming `%s' to `%s_%0*d_'.\n", it->first.c_str(), auto_prefix.c_str(), auto_name_digits, auto_name_offset + it->second);
log(" renaming `%s' to `%s_%0*d_'.\n", it->first, auto_prefix, auto_name_digits, auto_name_offset + it->second);
}
std::string next_auto_id()
@ -494,7 +494,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
std::ofstream extmem_f(extmem_filename, std::ofstream::trunc);
if (extmem_f.fail())
log_error("Can't open file `%s' for writing: %s\n", extmem_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", extmem_filename, strerror(errno));
else
{
Const data = mem.get_init_data();
@ -2632,7 +2632,7 @@ struct VerilogBackend : public Backend {
log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name));
continue;
}
log("Dumping module `%s'.\n", module->name.c_str());
log("Dumping module `%s'.\n", module->name);
module->sort();
dump_module(*f, "", module);
}

2
docs/source/code_examples/extensions/my_cmd.cc
View file

@ -10,7 +10,7 @@ struct MyPass : public Pass {
{
log("Arguments to my_cmd:\n");
for (auto &arg : args)
log(" %s\n", arg.c_str());
log(" %s\n", arg);
log("Modules in current design:\n");
for (auto mod : design->modules())

2
docs/source/code_examples/functional/dummy.cc
View file

@ -16,7 +16,7 @@ struct FunctionalDummyBackend : public Backend {
for (auto module : design->selected_modules())
{
log("Processing module `%s`.\n", module->name.c_str());
log("Processing module `%s`.\n", module->name);
// convert module to FunctionalIR
auto ir = Functional::IR::from_module(module);

6
docs/source/yosys_internals/hashing.rst
View file

@ -45,9 +45,9 @@ creates a bijective map from ``K`` to the integers. For example:
log("%d\n", si("world")); // will print 43
log("%d\n", si.at("world")); // will print 43
log("%d\n", si.at("dummy")); // will throw exception
log("%s\n", si[42].c_str())); // will print hello
log("%s\n", si[43].c_str())); // will print world
log("%s\n", si[44].c_str())); // will throw exception
log("%s\n", si[42])); // will print hello
log("%s\n", si[43])); // will print world
log("%s\n", si[44])); // will throw exception
It is not possible to remove elements from an idict.

4
examples/cxx-api/scopeinfo_example.cc
View file

@ -77,9 +77,9 @@ struct ScopeinfoExamplePass : public Pass {
continue;
}
log("%s %s\n", wire_scope.first.path_str().c_str(), log_id(wire_scope.second));
log("%s %s\n", wire_scope.first.path_str(), log_id(wire_scope.second));
for (auto src : index.sources(wire))
log(" - %s\n", src.c_str());
log(" - %s\n", src);
}
}
}

2
frontends/aiger/aigerparse.cc
View file

@ -909,7 +909,7 @@ void AigerReader::post_process()
module->rename(cell, escaped_s);
}
else
log_error("Symbol type '%s' not recognised.\n", type.c_str());
log_error("Symbol type '%s' not recognised.\n", type);
}
}

4
frontends/aiger2/xaiger.cc
View file

@ -91,7 +91,7 @@ struct Xaiger2Frontend : public Frontend {
std::ifstream map_file;
map_file.open(map_filename);
if (!map_file)
log_error("Failed to open map file '%s'\n", map_filename.c_str());
log_error("Failed to open map file '%s'\n", map_filename);
unsigned int M, I, L, O, A;
std::string header;
@ -388,7 +388,7 @@ struct Xaiger2Frontend : public Frontend {
if (f->eof())
break;
log_assert(!f->fail());
log("input file: %s\n", scratch.c_str());
log("input file: %s\n", scratch);
}
log_debug("co_counter=%d\n", co_counter);

24
frontends/ast/ast.cc
View file

@ -1108,9 +1108,9 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
if (defer)
log("Storing AST representation for module `%s'.\n", ast->str.c_str());
log("Storing AST representation for module `%s'.\n", ast->str);
else if (!quiet) {
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
log("Generating RTLIL representation for module `%s'.\n", ast->str);
}
AstModule *module = new AstModule;
@ -1411,7 +1411,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
for (auto& n : design->verilog_packages) {
for (auto &o : n->children) {
auto cloned_node = o->clone();
// log("cloned node %s\n", type2str(cloned_node->type).c_str());
// log("cloned node %s\n", type2str(cloned_node->type));
if (cloned_node->type == AST_ENUM) {
for (auto &e : cloned_node->children) {
log_assert(e->type == AST_ENUM_ITEM);
@ -1432,7 +1432,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
for (const auto& node : child->children)
if (node->type == AST_PARAMETER && param_has_no_default(node.get()))
{
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str());
log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str);
defer_local = true;
break;
}
@ -1507,7 +1507,7 @@ std::pair<std::string,std::string> AST::split_modport_from_type(std::string name
interface_modport = seglist[1];
}
else { // Erroneous port type
log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
log_error("More than two '.' in signal port type (%s)\n", name_type);
}
}
return std::pair<std::string,std::string>(interface_type, interface_modport);
@ -1720,7 +1720,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
new_subcell->set_bool_attribute(ID::is_interface);
}
else {
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
}
}
@ -1731,7 +1731,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
} else {
modname = new_modname;
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
@ -1750,7 +1750,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
process_module(design, new_ast.get(), false, NULL, quiet);
design->module(modname)->check();
} else if (!quiet) {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
log("Found cached RTLIL representation for module `%s'.\n", modname);
}
return modname;
@ -1799,14 +1799,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
auto it = parameters.find(child->str);
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
log("Parameter %s = %s\n", child->str, log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
it = parameters.find(stringf("$%d", para_counter));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
named_parameters.emplace_back(child->str, it->second);
continue;
}
@ -1839,13 +1839,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
auto it = parameters.find(child->str);
if (it != parameters.end()) {
if (!quiet)
log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second));
log("Parameter %s = %s\n", child->str, log_signal(it->second));
goto rewrite_parameter;
}
it = parameters.find(stringf("$%d", para_counter));
if (it != parameters.end()) {
if (!quiet)
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second));
log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second));
goto rewrite_parameter;
}
continue;

20
frontends/ast/dpicall.cc
View file

@ -40,7 +40,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
plugin_name = loaded_plugin_aliases.at(plugin_name);
if (loaded_plugins.count(plugin_name) == 0)
log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name.c_str(), plugin_name.c_str());
log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name, plugin_name);
void *symbol = dlsym(loaded_plugins.at(plugin_name), real_symbol_name.c_str());
@ -61,7 +61,7 @@ static ffi_fptr resolve_fn (std::string symbol_name)
if (symbol != nullptr)
return (ffi_fptr) symbol;
log_error("unable to resolve '%s'.\n", symbol_name.c_str());
log_error("unable to resolve '%s'.\n", symbol_name);
}
std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<std::unique_ptr<AST::AstNode>> &args)
@ -74,32 +74,32 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
ffi_cif cif;
int status;
log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str());
log("Calling DPI function `%s' and returning `%s':\n", fname, rtype);
log_assert(GetSize(args) == GetSize(argtypes));
for (int i = 0; i < GetSize(args); i++) {
if (argtypes[i] == "real") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
value_store[i].f64 = args[i]->asReal(args[i]->is_signed);
values[i] = &value_store[i].f64;
types[i] = &ffi_type_double;
} else if (argtypes[i] == "shortreal") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed));
value_store[i].f32 = args[i]->asReal(args[i]->is_signed);
values[i] = &value_store[i].f32;
types[i] = &ffi_type_double;
} else if (argtypes[i] == "integer") {
log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed));
log(" arg %d (%s): %lld\n", i, argtypes[i], (long long)args[i]->asInt(args[i]->is_signed));
value_store[i].i32 = args[i]->asInt(args[i]->is_signed);
values[i] = &value_store[i].i32;
types[i] = &ffi_type_sint32;
} else if (argtypes[i] == "chandle") {
log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false));
log(" arg %d (%s): %llx\n", i, argtypes[i], (unsigned long long)args[i]->asInt(false));
value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed);
values[i] = &value_store[i].ptr;
types[i] = &ffi_type_pointer;
} else {
log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i);
log_error("invalid argtype '%s' for argument %d.\n", argtypes[i], i);
}
}
@ -116,7 +116,7 @@ std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType loc, const std::string
types[args.size()] = &ffi_type_pointer;
values[args.size()] = &value_store[args.size()].ptr;
} else {
log_error("invalid rtype '%s'.\n", rtype.c_str());
log_error("invalid rtype '%s'.\n", rtype);
}
if ((status = ffi_prep_cif(&cif, FFI_DEFAULT_ABI, args.size(), types[args.size()], types.data())) != FFI_OK)
@ -155,7 +155,7 @@ YOSYS_NAMESPACE_BEGIN
std::unique_ptr<AST::AstNode> AST::dpi_call(AstSrcLocType, const std::string&, const std::string &fname, const std::vector<std::string>&, const std::vector<std::unique_ptr<AST::AstNode>>&)
{
log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str());
log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname);
}
YOSYS_NAMESPACE_END

2
frontends/ast/genrtlil.cc
View file

@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator
if (found_anyedge_syncs) {
if (found_global_syncs)
always->input_error("Found non-synthesizable event list!\n");
log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str());
log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string());
log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
}

26
frontends/ast/simplify.cc
View file

@ -180,10 +180,10 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
if (template_node->attributes.count(ID::enum_type)) {
//get reference to enum node:
std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
// log("enum_type=%s (count=%lu)\n", enum_type, current_scope.count(enum_type));
// log("current scope:\n");
// for (auto &it : current_scope)
// log(" %s\n", it.first.c_str());
// log(" %s\n", it.first);
log_assert(current_scope.count(enum_type) == 1);
AstNode *enum_node = current_scope.at(enum_type);
log_assert(enum_node->type == AST_ENUM);
@ -911,7 +911,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
#if 0
log("-------------\n");
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this);
log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename, location.begin.line, type2str(type), this);
log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n",
int(const_fold), int(stage), int(width_hint), int(sign_hint));
// dumpAst(nullptr, "> ");
@ -963,7 +963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
goto verbose_activate;
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
continue;
verbose_activate:
@ -978,7 +978,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
silent_activate:
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
// log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags));
mem2reg_set.insert(mem);
}
@ -1063,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
if (str.substr(0, 8) == "$display")
fmt.append_literal("\n");
log("%s", fmt.render().c_str());
log("%s", fmt.render());
}
return false;
@ -1499,7 +1499,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
break;
case AST_ENUM:
//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
//log("\nENUM %s: %d child %d\n", str, basic_prep, children[0]->basic_prep);
if (!basic_prep) {
for (auto& item_node : children) {
while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false))
@ -1590,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
}
default:
log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str());
log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type));
}
}
@ -2297,7 +2297,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
str = try_pop_module_prefix();
for (auto& node : current_scope_ast->children) {
//log("looking at mod scope child %s\n", type2str(node->type).c_str());
//log("looking at mod scope child %s\n", type2str(node->type));
switch (node->type) {
case AST_PARAMETER:
case AST_LOCALPARAM:
@ -2308,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
case AST_FUNCTION:
case AST_TASK:
case AST_DPI_FUNCTION:
//log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str());
//log("found child %s, %s\n", type2str(node->type), node->str);
if (str == node->str) {
//log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str());
//log("add %s, type %s to scope\n", str, type2str(node->type));
current_scope[node->str] = node.get();
}
break;
@ -2319,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
for (auto& enum_node : node->children) {
log_assert(enum_node->type==AST_ENUM_ITEM);
if (str == enum_node->str) {
//log("\nadding enum item %s to scope\n", str.c_str());
//log("\nadding enum item %s to scope\n", str);
current_scope[str] = enum_node.get();
}
}
@ -5404,7 +5404,7 @@ std::unique_ptr<AstNode> AstNode::eval_const_function(AstNode *fcall, bool must_
#if 0
log("-----------------------------------\n");
for (auto &it : variables)
log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val));
log("%20s %40s\n", it.first, log_signal(it.second.val));
stmt->dumpAst(nullptr, "stmt> ");
#endif
if (stmt->type == AST_WIRE)

2
frontends/blif/blifparse.cc
View file

@ -618,7 +618,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
error:
log_error("Syntax error in line %d!\n", line_count);
error_with_reason:
log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
log_error("Syntax error in line %d: %s\n", line_count, err_reason);
}
struct BlifFrontend : public Frontend {

4
frontends/json/jsonparse.cc
View file

@ -289,7 +289,7 @@ void json_parse_attr_param(dict<IdString, Const> &results, JsonNode *node)
void json_import(Design *design, string &modname, JsonNode *node)
{
log("Importing module %s from JSON tree.\n", modname.c_str());
log("Importing module %s from JSON tree.\n", modname);
Module *module = new RTLIL::Module;
module->name = RTLIL::escape_id(modname.c_str());
@ -367,7 +367,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->port_input = true;
port_wire->port_output = true;
} else
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str());
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string);
port_wire->port_id = port_id;

12
frontends/liberty/liberty.cc
View file

@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
std::string id = RTLIL::escape_id(std::string(expr, id_len));
if (!module->wires_.count(id))
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id));
expr += id_len;
return module->wires_.at(id);
@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend {
if (cell->id != "cell" || cell->args.size() != 1)
continue;
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name));
std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
parse_type_map(type_map, cell);
@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend {
{
if (!flag_ignore_miss_dir)
{
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name));
} else {
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0));
delete module;
goto skip_cell;
}
@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend {
if (node->id == "bus" && node->args.size() == 1)
{
if (flag_ignore_buses) {
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0));
delete module;
goto skip_cell;
}
@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
}
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name));
simple_comb_cell = false;

20
frontends/rpc/rpc_frontend.cc
View file

@ -167,7 +167,7 @@ struct RpcModule : RTLIL::Module {
std::string parameter_info;
for (auto &param : parameters) {
log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second)));
log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second)));
parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second)));
}
@ -180,7 +180,7 @@ struct RpcModule : RTLIL::Module {
derived_name = "$paramod" + stripped_name + parameter_info;
if (design->has(derived_name)) {
log("Found cached RTLIL representation for module `%s'.\n", derived_name.c_str());
log("Found cached RTLIL representation for module `%s'.\n", derived_name);
} else {
std::string command, input;
std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters);
@ -437,7 +437,7 @@ struct RpcFrontend : public Pass {
command_path_len_w = SearchPathW(/*lpPath=*/NULL, /*lpFileName=*/command_w.c_str(), /*lpExtension=*/L".exe", /*nBufferLength=*/0, /*lpBuffer=*/NULL, /*lpFilePart=*/NULL);
if (command_path_len_w == 0) {
log_error("SearchPathW failed: %s\n", get_last_error_str().c_str());
log_error("SearchPathW failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
command_path_w.resize(command_path_len_w - 1);
@ -448,19 +448,19 @@ struct RpcFrontend : public Pass {
pipe_attr.bInheritHandle = TRUE;
pipe_attr.lpSecurityDescriptor = NULL;
if (!CreatePipe(&send_r, &send_w, &pipe_attr, /*nSize=*/0)) {
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
log_error("CreatePipe failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!SetHandleInformation(send_w, HANDLE_FLAG_INHERIT, 0)) {
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!CreatePipe(&recv_r, &recv_w, &pipe_attr, /*nSize=*/0)) {
log_error("CreatePipe failed: %s\n", get_last_error_str().c_str());
log_error("CreatePipe failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
if (!SetHandleInformation(recv_r, HANDLE_FLAG_INHERIT, 0)) {
log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str());
log_error("SetHandleInformation failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
@ -470,7 +470,7 @@ struct RpcFrontend : public Pass {
startup_info.hStdError = GetStdHandle(STD_ERROR_HANDLE);
startup_info.dwFlags |= STARTF_USESTDHANDLES;
if (!CreateProcessW(/*lpApplicationName=*/command_path_w.c_str(), /*lpCommandLine=*/&command_line_w[0], /*lpProcessAttributes=*/NULL, /*lpThreadAttributes=*/NULL, /*bInheritHandles=*/TRUE, /*dwCreationFlags=*/0, /*lpEnvironment=*/NULL, /*lpCurrentDirectory=*/NULL, &startup_info, &proc_info)) {
log_error("CreateProcessW failed: %s\n", get_last_error_str().c_str());
log_error("CreateProcessW failed: %s\n", get_last_error_str());
goto cleanup_exec;
}
CloseHandle(proc_info.hProcess);
@ -550,7 +550,7 @@ cleanup_exec:
h = CreateFileW(path_w.c_str(), GENERIC_READ|GENERIC_WRITE, /*dwShareMode=*/0, /*lpSecurityAttributes=*/NULL, /*dwCreationDisposition=*/OPEN_EXISTING, /*dwFlagsAndAttributes=*/0, /*hTemplateFile=*/NULL);
if (h == INVALID_HANDLE_VALUE) {
log_error("CreateFileW failed: %s\n", get_last_error_str().c_str());
log_error("CreateFileW failed: %s\n", get_last_error_str());
goto cleanup_path;
}
@ -586,7 +586,7 @@ cleanup_path:
log_cmd_error("Failed to connect to RPC frontend.\n");
for (auto &module_name : server->get_module_names()) {
log("Linking module `%s'.\n", module_name.c_str());
log("Linking module `%s'.\n", module_name);
RpcModule *module = new RpcModule;
module->name = "$abstract\\" + module_name;
module->server = server;

2
frontends/rtlil/rtlil_frontend.cc
View file

@ -90,7 +90,7 @@ struct RTLILFrontend : public Frontend {
}
extra_args(f, filename, args, argidx);
log("Input filename: %s\n", filename.c_str());
log("Input filename: %s\n", filename);
RTLIL_FRONTEND::lexin = f;
RTLIL_FRONTEND::current_design = design;

24
frontends/verific/verific.cc
View file

@ -143,7 +143,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
else
log("%s%s\n", message_prefix.c_str(), message.c_str());
log("%s%s\n", message_prefix, message);
}
if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR))
verific_error_msg = message;
@ -250,7 +250,7 @@ static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
{
if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
return RTLIL::Const::from_string(val.substr(1,val.size()-2));
log_error("Error parsing VHDL %s.\n", typ.c_str());
log_error("Error parsing VHDL %s.\n", typ);
}
static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
@ -261,7 +261,7 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string
c.flags |= RTLIL::CONST_FLAG_SIGNED;
return c;
}
log_error("Error parsing VHDL %s.\n", typ.c_str());
log_error("Error parsing VHDL %s.\n", typ);
}
static const RTLIL::Const extract_vhdl_integer(std::string &val)
@ -2655,7 +2655,7 @@ struct VerificExtNets
cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
}
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str());
log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A), get_full_netlist_name(B));
}
void run(Netlist *nl)
@ -2679,17 +2679,17 @@ struct VerificExtNets
continue;
if (verific_verbose)
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name());
log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl), inst->Name(), port->Name());
Netlist *ext_nl = net->Owner();
if (verific_verbose)
log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str());
log(" external net owner: %s\n", get_full_netlist_name(ext_nl));
Netlist *ca_nl = find_common_ancestor(nl, ext_nl);
if (verific_verbose)
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str());
log(" common ancestor: %s\n", get_full_netlist_name(ca_nl));
Net *ca_net = route_up(net, !port->IsOutput(), ca_nl);
Net *new_net = ca_net;
@ -3038,7 +3038,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
}
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
@ -3060,7 +3060,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
verific_cleanup();
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
return top;
}
@ -3349,7 +3349,7 @@ struct VerificPass : public Pass {
char block[4096];
while (1) {
if (fgets(block, 4096, Frontend::current_script_file == nullptr? stdin : Frontend::current_script_file) == nullptr)
log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
log_error("Unexpected end of file in here document '%s'!\n", filename);
buffer += block;
if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
break;
@ -4232,7 +4232,7 @@ struct VerificPass : public Pass {
}
lines.sort();
for (auto &line : lines)
log("verific -cfg %s\n", line.c_str());
log("verific -cfg %s\n", line);
goto check_error;
}
@ -4291,7 +4291,7 @@ struct VerificPass : public Pass {
}
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
log_error("%s\n", verific_error_msg);
}
#else /* YOSYS_ENABLE_VERIFIC */

2
frontends/verific/verificsva.cc
View file

@ -1024,7 +1024,7 @@ struct VerificSvaImporter
[[noreturn]] void parser_error(std::string errmsg)
{
if (!importer->mode_keep)
log_error("%s", errmsg.c_str());
log_error("%s", errmsg);
log_warning("%s", errmsg.c_str());
throw ParserErrorException();
}

8
frontends/verilog/preproc.cc
View file

@ -242,7 +242,7 @@ struct arg_map_t
void add_arg(const std::string &name, const char *default_value)
{
if (find(name)) {
log_error("Duplicate macro arguments with name `%s'.\n", name.c_str());
log_error("Duplicate macro arguments with name `%s'.\n", name);
}
name_to_pos[name] = args.size();
@ -789,14 +789,14 @@ frontend_verilog_preproc(std::istream &f,
else if (ifdef_pass_level > 0)
ifdef_pass_level--;
else
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
continue;
}
if (tok == "`else") {
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;
@ -813,7 +813,7 @@ frontend_verilog_preproc(std::istream &f,
std::string name = next_token(true);
if (ifdef_fail_level == 0) {
if (ifdef_pass_level == 0)
log_error("Found %s outside of macro conditional branch!\n", tok.c_str());
log_error("Found %s outside of macro conditional branch!\n", tok);
ifdef_pass_level--;
ifdef_fail_level = 1;
ifdef_already_satisfied = true;

2
frontends/verilog/verilog_frontend.cc
View file

@ -497,7 +497,7 @@ struct VerilogFrontend : public Frontend {
if (!flag_nopp) {
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
if (flag_ppdump)
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc);
parse_state.lexin = new std::istringstream(code_after_preproc);
}

6
frontends/verilog/verilog_parser.y
View file

@ -3261,7 +3261,7 @@ basic_expr:
ConstParser p{@4};
auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
if (val == nullptr)
log_error("Value conversion failed: `%s'\n", $4->c_str());
log_error("Value conversion failed: `%s'\n", *$4);
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move($2), std::move(val));
} |
hierarchical_id integral_number {
@ -3274,7 +3274,7 @@ basic_expr:
auto val = p.const2ast(*$2, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
SET_AST_NODE_LOC(val.get(), @2, @2);
if (val == nullptr)
log_error("Value conversion failed: `%s'\n", $2->c_str());
log_error("Value conversion failed: `%s'\n", *$2);
$$ = std::make_unique<AstNode>(@$, AST_TO_BITS, std::move(bits), std::move(val));
} |
integral_number {
@ -3282,7 +3282,7 @@ basic_expr:
$$ = p.const2ast(*$1, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib);
SET_AST_NODE_LOC($$.get(), @1, @1);
if ($$ == nullptr)
log_error("Value conversion failed: `%s'\n", $1->c_str());
log_error("Value conversion failed: `%s'\n", *$1);
} |
TOK_REALVAL {
$$ = std::make_unique<AstNode>(@$, AST_REALVALUE);

10
kernel/driver.cc
View file

@ -585,7 +585,7 @@ int main(int argc, char **argv)
FILE *scriptfp = fopen(scriptfile.c_str(), "r");
if (scriptfp == nullptr) {
log_error("Failed to open file '%s' for reading.\n", scriptfile.c_str());
log_error("Failed to open file '%s' for reading.\n", scriptfile);
}
if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) {
log_flush();
@ -664,7 +664,7 @@ int main(int argc, char **argv)
log("Warnings: %d experimental features used (not excluded with -x).\n", GetSize(log_experimentals));
#ifdef _WIN32
log("End of script. Logfile hash: %s\n", hash.c_str());
log("End of script. Logfile hash: %s\n", hash);
#else
std::string meminfo;
std::string stats_divider = ", ";
@ -690,7 +690,7 @@ int main(int argc, char **argv)
meminfo = stringf(", MEM: %.2f MB peak",
ru_buffer.ru_maxrss / (1024.0 * 1024.0));
#endif
log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(),
log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash,
stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec,
ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec, meminfo.c_str());
#endif
@ -768,9 +768,9 @@ int main(int argc, char **argv)
f = fopen(filename.c_str(), "a+");
if (f == NULL)
log_error("Can't create coverage file `%s'.\n", filename.c_str());
log_error("Can't create coverage file `%s'.\n", filename);
log("<writing coverage file \"%s\">\n", filename.c_str());
log("<writing coverage file \"%s\">\n", filename);
for (auto &it : get_coverage_data())
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());

4
kernel/fstdata.cc
View file

@ -35,7 +35,7 @@ FstData::FstData(std::string filename) : ctx(nullptr)
filename_trim.erase(filename_trim.size()-4);
tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir(), filename_trim);
std::string cmd = stringf("vcd2fst %s %s", filename, tmp_file);
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
filename = tmp_file;
@ -44,7 +44,7 @@ FstData::FstData(std::string filename) : ctx(nullptr)
const std::vector<std::string> g_units = { "s", "ms", "us", "ns", "ps", "fs", "as", "zs" };
ctx = (fstReaderContext *)fstReaderOpen(filename.c_str());
if (!ctx)
log_error("Error opening '%s' as FST file\n", filename.c_str());
log_error("Error opening '%s' as FST file\n", filename);
int scale = (int)fstReaderGetTimescale(ctx);
timescale = pow(10.0, scale);
timescale_str = "";

12
kernel/functional.cc
View file

@ -395,7 +395,7 @@ public:
Node y = neg_if(y_flipped, sign(b));
return factory.extend(y, y_width, true);
} else
log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
log_error("unhandled cell in CellSimplifier %s\n", cellType);
} else {
if(cellType.in(ID($mod), ID($modfloor)))
return factory.extend(factory.unsigned_mod(a, b), y_width, false);
@ -458,9 +458,9 @@ public:
return factory.value(state);
}
} else if(cellType == ID($check)) {
log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName.c_str());
log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName);
} else {
log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str());
log_error("`%s' cells are not supported by the functional backend\n", cellType);
}
}
};
@ -744,7 +744,7 @@ void IR::topological_sort() {
log_warning("Combinational loop:\n");
for (int *i = begin; i != end; ++i) {
Node node(_graph[*i]);
log("- %s = %s\n", RTLIL::unescape_id(node.name()).c_str(), node.to_string().c_str());
log("- %s = %s\n", RTLIL::unescape_id(node.name()), node.to_string());
}
log("\n");
scc = true;
@ -836,7 +836,7 @@ void Writer::print_impl(const char *fmt, vector<std::function<void()>> &fns)
else
p = pe;
if(index >= fns.size())
log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt).c_str());
log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt));
fns[index]();
next_index = index + 1;
}
@ -844,7 +844,7 @@ void Writer::print_impl(const char *fmt, vector<std::function<void()>> &fns)
case '}':
p++;
if(*p != '}')
log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt).c_str());
log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt));
*os << '}';
break;
default:

6
kernel/functional.h
View file

@ -552,17 +552,17 @@ namespace Functional {
}
IRInput &add_input(IdString name, IdString kind, Sort sort) {
auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort)));
if (!inserted) log_error("input `%s` was re-defined", name.c_str());
if (!inserted) log_error("input `%s` was re-defined", name);
return it->second;
}
IROutput &add_output(IdString name, IdString kind, Sort sort) {
auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort)));
if (!inserted) log_error("output `%s` was re-defined", name.c_str());
if (!inserted) log_error("output `%s` was re-defined", name);
return it->second;
}
IRState &add_state(IdString name, IdString kind, Sort sort) {
auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort)));
if (!inserted) log_error("state `%s` was re-defined", name.c_str());
if (!inserted) log_error("state `%s` was re-defined", name);
return it->second;
}
Node value(IRInput const& input) {

2
kernel/gzip.cc
View file

@ -121,7 +121,7 @@ std::istream* uncompressed(const std::string filename, std::ios_base::openmode m
}
if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) {
#ifdef YOSYS_ENABLE_ZLIB
log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str());
log("Found gzip magic in file `%s', decompressing using zlib.\n", filename);
if (magic[2] != 8)
log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n",
filename.c_str(), unsigned(magic[2]));

16
kernel/log.cc
View file

@ -228,7 +228,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s
for (int c : header_count)
header_id += stringf("%s%d", header_id.empty() ? "" : ".", c);
log("%s. ", header_id.c_str());
log("%s. ", header_id);
log_formatted_string(format, std::move(str));
log_flush();
@ -237,7 +237,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s
if (log_hdump.count(header_id) && design != nullptr)
for (auto &filename : log_hdump.at(header_id)) {
log("Dumping current design to '%s'.\n", filename.c_str());
log("Dumping current design to '%s'.\n", filename);
if (yosys_xtrace)
IdString::xtrace_db_dump();
Pass::call(design, {"dump", "-o", filename});
@ -635,21 +635,21 @@ void log_module(RTLIL::Module *module, std::string indent)
{
std::stringstream buf;
RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false);
log("%s", buf.str().c_str());
log("%s", buf.str());
}
void log_cell(RTLIL::Cell *cell, std::string indent)
{
std::stringstream buf;
RTLIL_BACKEND::dump_cell(buf, indent, cell);
log("%s", buf.str().c_str());
log("%s", buf.str());
}
void log_wire(RTLIL::Wire *wire, std::string indent)
{
std::stringstream buf;
RTLIL_BACKEND::dump_wire(buf, indent, wire);
log("%s", buf.str().c_str());
log("%s", buf.str());
}
void log_check_expected()
@ -668,7 +668,7 @@ void log_check_expected()
auto check = [&](const std::string kind, std::string pattern, LogExpectedItem item) {
if (item.current_count == 0) {
log_warn_regexes.clear();
log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str());
log_error("Expected %s pattern '%s' not found !\n", kind, pattern);
}
if (item.current_count != item.expected_count) {
log_warn_regexes.clear();
@ -689,7 +689,7 @@ void log_check_expected()
auto check_err = [&](const std::string kind, std::string pattern, LogExpectedItem item) {
if (item.current_count == item.expected_count) {
log_warn_regexes.clear();
log("Expected %s pattern '%s' found !!!\n", kind.c_str(), pattern.c_str());
log("Expected %s pattern '%s' found !!!\n", kind, pattern);
yosys_shutdown();
#ifdef EMSCRIPTEN
throw 0;
@ -700,7 +700,7 @@ void log_check_expected()
#endif
} else {
log_warn_regexes.clear();
log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str());
log_error("Expected %s pattern '%s' not found !\n", kind, pattern);
}
};
for (auto &[pattern, item] : expect_error)

2
kernel/log.h
View file

@ -424,7 +424,7 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false")
static inline void log_dump_val_worker(double v) { log("%f", v); }
static inline void log_dump_val_worker(char *v) { log("%s", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }
static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
static inline void log_dump_val_worker(std::string v) { log("%s", v); }
static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
void log_dump_val_worker(RTLIL::IdString v);

6
kernel/log_help.cc
View file

@ -85,7 +85,7 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead
if (leading_newline)
log("\n");
for (std::string line; std::getline(iss, line);) {
log("%s", indent_str.c_str());
log("%s", indent_str);
auto curr_len = indent_str.length();
std::istringstream lss(line);
for (std::string word; std::getline(lss, word, ' ');) {
@ -93,10 +93,10 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead
word = word.substr(1, word.length()-2);
if (curr_len + word.length() >= MAX_LINE_LEN-1) {
curr_len = 0;
log("\n%s", indent_str.c_str());
log("\n%s", indent_str);
}
if (word.length()) {
log("%s ", word.c_str());
log("%s ", word);
curr_len += word.length() + 1;
}
}

64
kernel/register.cc
View file

@ -54,7 +54,7 @@ Pass::Pass(std::string name, std::string short_help, source_location location) :
void Pass::run_register()
{
if (pass_register.count(pass_name) && !replace_existing_pass())
log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str());
log_error("Unable to register pass '%s', pass already exists!\n", pass_name);
pass_register[pass_name] = this;
}
@ -123,7 +123,7 @@ void Pass::help()
prettyHelp.log_help();
} else {
log("\n");
log("No help message for command `%s'.\n", pass_name.c_str());
log("No help message for command `%s'.\n", pass_name);
log("\n");
}
}
@ -143,7 +143,7 @@ void Pass::cmd_log_args(const std::vector<std::string> &args)
return;
log("Full command line:");
for (size_t i = 0; i < args.size(); i++)
log(" %s", args[i].c_str());
log(" %s", args[i]);
log("\n");
}
@ -158,7 +158,7 @@ void Pass::cmd_error(const std::vector<std::string> &args, size_t argidx, std::s
command_text = command_text + (command_text.empty() ? "" : " ") + args[i];
}
log("\nSyntax error in command `%s':\n", command_text.c_str());
log("\nSyntax error in command `%s':\n", command_text);
help();
log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n",
@ -257,7 +257,7 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
if (echo_mode) {
log("%s", create_prompt(design, 0));
for (size_t i = 0; i < args.size(); i++)
log("%s%s", i ? " " : "", args[i].c_str());
log("%s%s", i ? " " : "", args[i]);
log("\n");
}
@ -330,9 +330,9 @@ bool ScriptPass::check_label(std::string label, std::string info)
if (active_design == nullptr) {
log("\n");
if (info.empty())
log(" %s:\n", label.c_str());
log(" %s:\n", label);
else
log(" %s: %s\n", label.c_str(), info.c_str());
log(" %s: %s\n", label, info);
return true;
} else {
if (!active_run_from.empty() && active_run_from == active_run_to) {
@ -351,9 +351,9 @@ void ScriptPass::run(std::string command, std::string info)
{
if (active_design == nullptr) {
if (info.empty())
log(" %s\n", command.c_str());
log(" %s\n", command);
else
log(" %s %s\n", command.c_str(), info.c_str());
log(" %s %s\n", command, info);
} else {
Pass::call(active_design, command);
active_design->check();
@ -364,9 +364,9 @@ void ScriptPass::run_nocheck(std::string command, std::string info)
{
if (active_design == nullptr) {
if (info.empty())
log(" %s\n", command.c_str());
log(" %s\n", command);
else
log(" %s %s\n", command.c_str(), info.c_str());
log(" %s %s\n", command, info);
} else {
Pass::call(active_design, command);
}
@ -402,11 +402,11 @@ Frontend::Frontend(std::string name, std::string short_help, source_location loc
void Frontend::run_register()
{
if (pass_register.count(pass_name) && !replace_existing_pass())
log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str());
log_error("Unable to register pass '%s', pass already exists!\n", pass_name);
pass_register[pass_name] = this;
if (frontend_register.count(frontend_name) && !replace_existing_pass())
log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name.c_str());
log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name);
frontend_register[frontend_name] = this;
}
@ -462,7 +462,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
char block[4096];
while (1) {
if (fgets(block, 4096, Frontend::current_script_file == nullptr? stdin : Frontend::current_script_file) == nullptr)
log_error("Unexpected end of file in here document '%s'!\n", filename.c_str());
log_error("Unexpected end of file in here document '%s'!\n", filename);
buffer += block;
if (buffer.size() > 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r'))
break;
@ -548,11 +548,11 @@ Backend::Backend(std::string name, std::string short_help, source_location locat
void Backend::run_register()
{
if (pass_register.count(pass_name))
log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str());
log_error("Unable to register pass '%s', pass already exists!\n", pass_name);
pass_register[pass_name] = this;
if (backend_register.count(backend_name))
log_error("Unable to register backend '%s', backend already exists!\n", backend_name.c_str());
log_error("Unable to register backend '%s', backend already exists!\n", backend_name);
backend_register[backend_name] = this;
}
@ -699,12 +699,12 @@ static void log_warning_flags(Pass *pass) {
if (pass->experimental_flag) {
if (!has_warnings) log("\n");
has_warnings = true;
log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name.c_str());
log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name);
}
if (pass->internal_flag) {
if (!has_warnings) log("\n");
has_warnings = true;
log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name.c_str());
log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name);
}
if (has_warnings)
log("\n");
@ -966,7 +966,7 @@ struct HelpPass : public Pass {
auto cell_pair = pair<SimHelper, CellType>(cell_help, it.second);
cells.emplace(name, cell_pair);
} else {
log("ERROR: Missing cell help for cell '%s'.\n", name.c_str());
log("ERROR: Missing cell help for cell '%s'.\n", name);
raise_error |= true;
}
}
@ -1028,7 +1028,7 @@ struct HelpPass : public Pass {
if (args.size() == 1) {
log("\n");
for (auto &it : pass_register)
log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str());
log(" %-20s %s\n", it.first, it.second->short_help);
log("\n");
log("Type 'help <command>' for more information on a command.\n");
log("Type 'help -cells' for a list of all cell types.\n");
@ -1040,7 +1040,7 @@ struct HelpPass : public Pass {
if (args[1] == "-all") {
for (auto &it : pass_register) {
log("\n\n");
log("%s -- %s\n", it.first.c_str(), it.second->short_help.c_str());
log("%s -- %s\n", it.first, it.second->short_help);
for (size_t i = 0; i < it.first.size() + it.second->short_help.size() + 6; i++)
log("=");
log("\n");
@ -1052,7 +1052,7 @@ struct HelpPass : public Pass {
log("\n");
for (auto &it : cell_help_messages.cell_help) {
SimHelper help_cell = it.second;
log(" %-15s %s\n", help_cell.name.c_str(), help_cell.ports.c_str());
log(" %-15s %s\n", help_cell.name, help_cell.ports);
}
log("\n");
log("Type 'help <cell_type>' for more information on a cell type.\n");
@ -1067,34 +1067,34 @@ struct HelpPass : public Pass {
auto help_cell = cell_help_messages.get(args[1]);
if (is_code_getter(args[1])) {
log("\n");
log("%s\n", help_cell.code.c_str());
log("%s\n", help_cell.code);
} else {
log("\n %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str());
log("\n %s %s\n\n", help_cell.name, help_cell.ports);
if (help_cell.ver == "2" || help_cell.ver == "2a") {
if (help_cell.title != "") log("%s:\n", help_cell.title.c_str());
if (help_cell.title != "") log("%s:\n", help_cell.title);
std::stringstream ss;
ss << help_cell.desc;
for (std::string line; std::getline(ss, line, '\n');) {
if (line != "::") log("%s\n", line.c_str());
if (line != "::") log("%s\n", line);
}
} else if (help_cell.desc.length()) {
log("%s\n", help_cell.desc.c_str());
log("%s\n", help_cell.desc);
} else {
log("No help message for this cell type found.\n");
}
log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1]);
log("\n");
}
}
else
log("No such command or cell type: %s\n", args[1].c_str());
log("No such command or cell type: %s\n", args[1]);
return;
} else if (args.size() == 3) {
// this option is undocumented as it is for internal use only
if (args[1] == "-dump-cmds-json") {
PrettyJson json;
if (!json.write_to_file(args[2]))
log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno));
if (dump_cmds_json(json)) {
log_abort();
}
@ -1103,13 +1103,13 @@ struct HelpPass : public Pass {
else if (args[1] == "-dump-cells-json") {
PrettyJson json;
if (!json.write_to_file(args[2]))
log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno));
if (dump_cells_json(json)) {
log_error("One or more cells defined in celltypes.h are missing help documentation.\n");
}
}
else
log("Unknown help command: `%s %s'\n", args[1].c_str(), args[2].c_str());
log("Unknown help command: `%s %s'\n", args[1], args[2]);
return;
}

2
kernel/rtlil.cc
View file

@ -1056,7 +1056,7 @@ void RTLIL::Design::add(RTLIL::Binding *binding)
RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
{
if (modules_.count(name) != 0)
log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name);
log_assert(refcount_modules_ == 0);
RTLIL::Module *module = new RTLIL::Module;

2
kernel/sexpr.cc
View file

@ -119,7 +119,7 @@ void SExprWriter::print(SExpr const &sexpr, bool close, bool indent_rest) {
_pending_nl = true;
}
}else
log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string().c_str());
log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string());
}
void SExprWriter::close(size_t n) {

2
kernel/tclapi.cc
View file

@ -87,7 +87,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
tcl_command_name = "renames";
Tcl_CmdInfo info;
if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) {
log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str());
log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first);
} else {
std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name, it.first);
Tcl_Eval(interp, tcl_script.c_str());

18
kernel/yosys.cc
View file

@ -710,7 +710,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
} else if (filename == "-") {
command = "script";
} else {
log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str());
log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename);
}
}
@ -731,7 +731,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
from_to_active = run_from.empty();
}
log("\n-- Executing script file `%s' --\n", filename.c_str());
log("\n-- Executing script file `%s' --\n", filename);
FILE *f = stdin;
@ -741,7 +741,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
}
if (f == NULL)
log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno));
log_error("Can't open script file `%s' for reading: %s\n", filename, strerror(errno));
FILE *backup_script_file = Frontend::current_script_file;
Frontend::current_script_file = f;
@ -790,9 +790,9 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi
}
if (filename == "-") {
log("\n-- Parsing stdin using frontend `%s' --\n", command.c_str());
log("\n-- Parsing stdin using frontend `%s' --\n", command);
} else {
log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str());
log("\n-- Parsing `%s' using frontend `%s' --\n", filename, command);
}
if (command[0] == ' ') {
@ -811,7 +811,7 @@ void run_pass(std::string command, RTLIL::Design *design)
if (design == nullptr)
design = yosys_design;
log("\n-- Running command `%s' --\n", command.c_str());
log("\n-- Running command `%s' --\n", command);
Pass::call(design, command);
}
@ -843,16 +843,16 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig
else if (filename.empty())
return;
else
log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename.c_str());
log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename);
}
if (filename.empty())
filename = "-";
if (filename == "-") {
log("\n-- Writing to stdout using backend `%s' --\n", command.c_str());
log("\n-- Writing to stdout using backend `%s' --\n", command);
} else {
log("\n-- Writing to `%s' using backend `%s' --\n", filename.c_str(), command.c_str());
log("\n-- Writing to `%s' using backend `%s' --\n", filename, command);
}
Backend::backend_call(design, NULL, filename, command);

30
kernel/yw.cc
View file

@ -108,38 +108,38 @@ ReadWitness::ReadWitness(const std::string &filename) :
{
std::ifstream f(filename.c_str());
if (f.fail() || GetSize(filename) == 0)
log_error("Cannot open file `%s`\n", filename.c_str());
log_error("Cannot open file `%s`\n", filename);
std::stringstream buf;
buf << f.rdbuf();
std::string err;
json11::Json json = json11::Json::parse(buf.str(), err);
if (!err.empty())
log_error("Failed to parse `%s`: %s\n", filename.c_str(), err.c_str());
log_error("Failed to parse `%s`: %s\n", filename, err);
std::string format = json["format"].string_value();
if (format.empty())
log_error("Failed to parse `%s`: Unknown format\n", filename.c_str());
log_error("Failed to parse `%s`: Unknown format\n", filename);
if (format != "Yosys Witness Trace")
log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename.c_str(), format.c_str());
log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename, format);
for (auto &clock_json : json["clocks"].array_items()) {
Clock clock;
clock.path = get_path(clock_json["path"]);
if (clock.path.empty())
log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename, clock_json.dump());
auto edge_str = clock_json["edge"];
if (edge_str.string_value() == "posedge")
clock.is_posedge = true;
else if (edge_str.string_value() == "negedge")
clock.is_negedge = true;
else
log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename, clock_json.dump());
if (!clock_json["offset"].is_number())
log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename, clock_json.dump());
clock.offset = clock_json["offset"].int_value();
if (clock.offset < 0)
log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str());
log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename, clock_json.dump());
clocks.push_back(clock);
}
@ -149,18 +149,18 @@ ReadWitness::ReadWitness(const std::string &filename) :
signal.bits_offset = bits_offset;
signal.path = get_path(signal_json["path"]);
if (signal.path.empty())
log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename, signal_json.dump());
if (!signal_json["width"].is_number())
log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename, signal_json.dump());
signal.width = signal_json["width"].int_value();
if (signal.width < 0)
log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename, signal_json.dump());
bits_offset += signal.width;
if (!signal_json["offset"].is_number())
log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename, signal_json.dump());
signal.offset = signal_json["offset"].int_value();
if (signal.offset < 0)
log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str());
log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename, signal_json.dump());
signal.init_only = signal_json["init_only"].bool_value();
signals.push_back(signal);
}
@ -168,11 +168,11 @@ ReadWitness::ReadWitness(const std::string &filename) :
for (auto &step_json : json["steps"].array_items()) {
Step step;
if (!step_json["bits"].is_string())
log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename.c_str(), GetSize(steps));
log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename, GetSize(steps));
step.bits = step_json["bits"].string_value();
for (char c : step.bits) {
if (c != '0' && c != '1' && c != 'x' && c != '?')
log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename.c_str(), c, GetSize(steps));
log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename, c, GetSize(steps));
}
steps.push_back(step);
}

2
passes/cmds/abstract.cc
View file

@ -67,7 +67,7 @@ struct Slice {
int wire_offset(RTLIL::Wire *wire, int index) const {
int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index);
if (rtl_offset < 0 || rtl_offset >= wire->width) {
log_error("Slice %s is out of bounds for wire %s in module %s", to_string().c_str(), log_id(wire), log_id(wire->module));
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module));
}
return rtl_offset;
}

14
passes/cmds/add.cc
View file

@ -38,22 +38,22 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_assert(is_formal_celltype(celltype));
if (wire == nullptr) {
log_error("Could not find wire with name \"%s\".\n", name.c_str());
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
RTLIL::Wire *enable_wire = module->wire(escaped_enable_name);
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}
}
@ -79,7 +79,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (wire == nullptr)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name);
}
else
{
@ -91,7 +91,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
if (!flag_global)
@ -110,7 +110,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
cell->setPort(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str());
log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type);
}
}

2
passes/cmds/cover.cc
View file

@ -146,7 +146,7 @@ struct CoverPass : public Pass {
for (auto f : out_files)
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
if (do_log)
log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
log("%-60s %10d %s\n", it.second.first, it.second.second, it.first);
}
#else
for (auto f : out_files)

2
passes/cmds/edgetypes.cc
View file

@ -105,7 +105,7 @@ struct EdgetypePass : public Pass {
edge_cache.sort();
for (auto &str : edge_cache)
log("%s\n", str.c_str());
log("%s\n", str);
}
} EdgetypePass;

2
passes/cmds/exec.cc
View file

@ -172,7 +172,7 @@ struct ExecPass : public Pass {
std::string line = linebuf.substr(0, pos);
linebuf.erase(0, pos + 1);
if (!flag_quiet)
log("%s\n", line.c_str());
log("%s\n", line);
if (flag_expect_stdout)
for(auto &x : expect_stdout)

2
passes/cmds/glift.cc
View file

@ -343,7 +343,7 @@ private:
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
log("Adding cell %s\n", cell_module_def->name.c_str());
log("Adding cell %s\n", cell_module_def->name);
for (auto &it : orig_ports) {
RTLIL::SigSpec port = it.second;
RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);

8
passes/cmds/internal_stats.cc
View file

@ -100,15 +100,15 @@ struct InternalStatsPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
if (auto mem = current_mem_bytes()) {
log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str());
log(" \"memory_now\": %s,\n", std::to_string(*mem));
}
auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode);
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str());
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes));
}
// stats go here

4
passes/cmds/linecoverage.cc
View file

@ -85,7 +85,7 @@ struct CoveragePass : public Pass {
if (!ofile.empty()) {
fout.open(ofile, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", ofile.c_str());
log_error("Could not open file \"%s\" with write access.\n", ofile);
}
std::map<std::string, std::set<int>> uncovered_lines;
@ -128,7 +128,7 @@ struct CoveragePass : public Pass {
for (const auto& file_entry : all_lines) {
int lines_found = file_entry.second.size();
int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0);
log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found);
log("File %s: %d/%d lines covered\n", file_entry.first, lines_hit, lines_found);
if(!ofile.empty()) {
fout << "SF:" << file_entry.first << "\n";

2
passes/cmds/logcmd.cc
View file

@ -106,7 +106,7 @@ struct LogPass : public Pass {
if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end);
if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end);
if (to_log) {
if (!header) log("%s%s", text.c_str(), line_end);
if (!header) log("%s%s", text, line_end);
else log_header(design, "%s%s", text.c_str(), line_end);
}
}

8
passes/cmds/logger.cc
View file

@ -108,7 +108,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to warn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to warn list.\n", pattern);
log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -120,7 +120,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to nowarn list.\n", pattern);
log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -132,7 +132,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to werror list.\n", pattern.c_str());
log("Added regex '%s' for warnings to werror list.\n", pattern);
log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -152,7 +152,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-experimental" && argidx+1 < args.size()) {
std::string value = args[++argidx];
log("Added '%s' experimental ignore list.\n", value.c_str());
log("Added '%s' experimental ignore list.\n", value);
log_experimentals_ignored.insert(value);
continue;
}

6
passes/cmds/plugin.cc
View file

@ -187,11 +187,11 @@ struct PluginPass : public Pass {
log("Loaded plugins:\n");
for (auto &it : loaded_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#ifdef WITH_PYTHON
for (auto &it : loaded_python_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#endif
if (!loaded_plugin_aliases.empty()) {
@ -200,7 +200,7 @@ struct PluginPass : public Pass {
for (auto &it : loaded_plugin_aliases)
max_alias_len = max(max_alias_len, GetSize(it.first));
for (auto &it : loaded_plugin_aliases)
log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
log("Alias: %-*s %s\n", max_alias_len, it.first, it.second);
}
}
}

2
passes/cmds/portarcs.cc
View file

@ -278,7 +278,7 @@ struct PortarcsPass : Pass {
log("\n");
for (auto bit : outputs) {
log(" %10s ", bit_str(bit).c_str());
log(" %10s ", bit_str(bit));
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++)
log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay);

2
passes/cmds/portlist.cc
View file

@ -75,7 +75,7 @@ struct PortlistPass : public Pass {
}
log("module %s%s\n", log_id(module), m_mode ? " (" : "");
for (int i = 0; i < GetSize(ports); i++)
log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
if (m_mode)
log(");\nendmodule\n");
};

10
passes/cmds/printattrs.cc
View file

@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string());
else
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name));
log("%s%s\n", get_indent_str(indent), log_id(mod->name));
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name));
log("%s%s\n", get_indent_str(indent), log_id(cell->name));
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass {
}
for (auto wire : mod->selected_wires()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name));
log("%s%s\n", get_indent_str(indent), log_id(wire->name));
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);

6
passes/cmds/rename.cc
View file

@ -577,7 +577,7 @@ struct RenamePass : public Pass {
new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_wire_names[wire].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename wire %s -> %s\n", name, new_name);
}
for (auto cell : module->selected_cells()) {
@ -590,7 +590,7 @@ struct RenamePass : public Pass {
new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_cell_names[cell].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename cell %s -> %s\n", name, new_name);
}
for (auto &it : new_wire_names)
@ -629,7 +629,7 @@ struct RenamePass : public Pass {
if (module_to_rename != nullptr) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
log("Renaming module %s to %s.\n", module_to_rename->name, to_name);
design->rename(module_to_rename, to_name);
} else
log_cmd_error("Object `%s' not found!\n", from_name.c_str());

2
passes/cmds/scc.cc
View file

@ -101,7 +101,7 @@ struct SccWorker
design(design), module(module), sigmap(module)
{
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}

18
passes/cmds/scratchpad.cc
View file

@ -76,18 +76,18 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-get" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier)) {
log("%s\n", design->scratchpad_get_string(identifier).c_str());
log("%s\n", design->scratchpad_get_string(identifier));
} else if (RTLIL::constpad.count(identifier)) {
log("%s\n", RTLIL::constpad.at(identifier).c_str());
log("%s\n", RTLIL::constpad.at(identifier));
} else {
log("\"%s\" not set\n", identifier.c_str());
log("\"%s\" not set\n", identifier);
}
continue;
}
if (args[argidx] == "-set" && argidx+2 < args.size()) {
string identifier = args[++argidx];
if (RTLIL::constpad.count(identifier))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier);
string value = args[++argidx];
if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2);
design->scratchpad_set_string(identifier, value);
@ -107,9 +107,9 @@ struct ScratchpadPass : public Pass {
else if (RTLIL::constpad.count(identifier_from))
value = RTLIL::constpad.at(identifier_from);
else
log_error("\"%s\" not set\n", identifier_from.c_str());
log_error("\"%s\" not set\n", identifier_from);
if (RTLIL::constpad.count(identifier_to))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to);
design->scratchpad_set_string(identifier_to, value);
continue;
}
@ -118,7 +118,7 @@ struct ScratchpadPass : public Pass {
string expected = args[++argidx];
if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2);
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
string value = design->scratchpad_get_string(identifier);
if (value != expected) {
log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n",
@ -129,13 +129,13 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-assert-set" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
continue;
}
if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) > 0)
log_error("scratchpad entry '%s' is defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is defined\n", identifier);
continue;
}
break;

16
passes/cmds/select.cc
View file

@ -632,20 +632,20 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
if (rule.cell_types.size() > 0) {
log(" cell types:");
for (auto &it : rule.cell_types)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
if (rule.port_names.size() > 0) {
log(" port names:");
for (auto &it : rule.port_names)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
}
if (limits.size() > 0) {
log(" limits:");
for (auto &it : limits)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
#endif
@ -1443,7 +1443,7 @@ struct SelectPass : public Pass {
std::ifstream f(read_file);
yosys_input_files.insert(read_file);
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
log_error("Can't open '%s' for reading: %s\n", read_file, strerror(errno));
auto sel = RTLIL::Selection::EmptySelection(design);
string line;
@ -1518,7 +1518,7 @@ struct SelectPass : public Pass {
f = fopen(write_file.c_str(), "w");
yosys_output_files.insert(write_file);
if (f == nullptr)
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
log_error("Can't open '%s' for writing: %s\n", write_file, strerror(errno));
}
if (work_stack.size() > 0)
design->push_selection(work_stack.back());
@ -1573,7 +1573,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1588,7 +1588,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1645,7 +1645,7 @@ struct SelectPass : public Pass {
if (!unset_name.empty())
{
if (!design->selection_vars.erase(unset_name))
log_error("Selection '%s' does not exist!\n", unset_name.c_str());
log_error("Selection '%s' does not exist!\n", unset_name);
return;
}

6
passes/cmds/setundef.cc
View file

@ -41,7 +41,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
if (module->count_id(name) != 0)
{
log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
log("Module %s already has such an object %s.\n", module->name, name);
name += "$";
return add_wire(module, name, width, flag_input, flag_output);
}
@ -56,7 +56,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
return wire;
@ -319,7 +319,7 @@ struct SetundefPass : public Pass {
wire = add_wire(module, name, c.width, true, false);
module->connect(RTLIL::SigSig(c, wire));
}
log("Exposing undriven wire %s as input.\n", wire->name.c_str());
log("Exposing undriven wire %s as input.\n", wire->name);
}
module->fixup_ports();
}

12
passes/cmds/show.cc
View file

@ -188,7 +188,7 @@ struct ShowWorker
if (enumerateIds) {
if (autonames.count(id) == 0) {
autonames[id] = autonames.size() + 1;
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str());
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id);
}
id = stringf("_%d_", autonames[id]);
} else if (abbreviateIds) {
@ -895,7 +895,7 @@ struct ShowPass : public Pass {
f.open(filename.c_str());
yosys_input_files.insert(filename);
if (f.fail())
log_error("Can't open lib file `%s'.\n", filename.c_str());
log_error("Can't open lib file `%s'.\n", filename);
RTLIL::Design *lib = new RTLIL::Design;
Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
libs.push_back(lib);
@ -907,7 +907,7 @@ struct ShowPass : public Pass {
std::string dot_file = stringf("%s.dot", prefix);
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = fopen(dot_file.c_str(), "w");
if (custom_prefix)
yosys_output_files.insert(dot_file);
@ -934,7 +934,7 @@ struct ShowPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -954,7 +954,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -964,7 +964,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

2
passes/cmds/splice.cc
View file

@ -345,7 +345,7 @@ struct SplicePass : public Pass {
for (auto module : design->selected_modules())
{
if (module->processes.size()) {
log("Skipping module %s as it contains processes.\n", module->name.c_str());
log("Skipping module %s as it contains processes.\n", module->name);
continue;
}

74
passes/cmds/stat.cc
View file

@ -285,7 +285,7 @@ struct statdata_t {
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
}
} else {
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type.c_str(),
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type,
(int)cell_data.double_parameter_area.size());
}
}
@ -452,22 +452,22 @@ struct statdata_t {
if (print_area) {
if (print_hierarchical) {
log(" %s %s %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), count_local_str.c_str(),
log(" %s %s %s %s %s%s\n", count_global_str, area_global_str, count_local_str,
area_local_str.c_str(), indent.c_str(), name.c_str());
} else if (print_global_only) {
log(" %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, area_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s %s%s\n", count_local_str.c_str(), area_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_local_str, area_local_str, indent, name);
}
} else {
if (print_hierarchical) {
log(" %s %s %s%s\n", count_global_str.c_str(), count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, count_local_str, indent, name);
} else if (print_global_only) {
log(" %s %s%s\n", count_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s%s\n", count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_local_str, indent, name);
}
}
}
@ -540,13 +540,13 @@ struct statdata_t {
if (!unknown_cell_area.empty()) {
log("\n");
for (auto cell_type : unknown_cell_area)
log(" Area for cell type %s is unknown!\n", cell_type.c_str());
log(" Area for cell type %s is unknown!\n", cell_type);
}
if (area != 0) {
log("\n");
if (print_hierarchical || print_global_only) {
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area);
log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area);
} else {
double local_area = 0;
@ -555,7 +555,7 @@ struct statdata_t {
double local_sequential_area = 0;
for (auto &it : local_seq_area_cells_by_type)
local_sequential_area += it.second;
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area);
log(" of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area,
100.0 * local_sequential_area / local_area);
}
@ -587,19 +587,19 @@ struct statdata_t {
if (!first_module)
log(",\n");
if (hierarchical) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0).c_str());
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0).c_str());
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0).c_str());
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0).c_str());
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0).c_str());
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0).c_str());
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0).c_str());
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0).c_str());
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0).c_str());
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area).c_str());
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area).c_str());
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area).c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0));
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0));
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0));
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0));
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0));
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0));
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0));
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0));
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0));
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area));
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area));
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area));
log(" \"num_cells_by_type\": {\n");
bool first_line = true;
@ -607,7 +607,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
area_cells_by_type.at(it.first))
@ -621,7 +621,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(0, 0, it.second,
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
.c_str());
@ -640,7 +640,7 @@ struct statdata_t {
} else {
if (global_only) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", num_wires);
log(" \"num_wire_bits\": %u,\n", num_wire_bits);
log(" \"num_pub_wires\": %u,\n", num_pub_wires);
@ -662,20 +662,20 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
log(" }");
} else {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", local_num_wires);
log(" \"num_wire_bits\": %u,\n", local_num_wire_bits);
log(" \"num_pub_wires\": %u,\n", local_num_pub_wires);
@ -697,14 +697,14 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
@ -824,11 +824,11 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
double value = std::stod(s);
single_parameter_area.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse single parameter area value '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse single parameter area value '%s': %s\n", s, e.what());
}
}
if (single_parameter_area.size() == 0)
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1].c_str());
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1]);
// check if it is a double parameterised area
}
const LibertyAst *dar = cell->find("double_area_parameterised");
@ -857,12 +857,12 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
value = std::stod(s);
cast_sub_array.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse double parameter area value for '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse double parameter area value for '%s': %s\n", s, e.what());
}
}
double_parameter_area.push_back(cast_sub_array);
if (cast_sub_array.size() == 0)
log_error("double paramter array has size 0: %s\n", s.c_str());
log_error("double paramter array has size 0: %s\n", s);
}
}
const LibertyAst *par = cell->find("port_names");
@ -973,10 +973,10 @@ struct StatPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
log(" \"modules\": {\n");
}

4
passes/cmds/timeest.cc
View file

@ -322,7 +322,7 @@ struct EstimateSta {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str());
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src);
printed.insert(cell);
}
} else {
@ -333,7 +333,7 @@ struct EstimateSta {
std::string src_attr = bit.wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr);
}
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]);
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src, levels[node]);
}
}

8
passes/cmds/viz.cc
View file

@ -988,7 +988,7 @@ struct VizPass : public Pass {
if (custom_prefix)
yosys_output_files.insert(dot_file);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = nullptr;
auto open_dot_file = [&]() {
if (f != nullptr) return;
@ -1028,7 +1028,7 @@ struct VizPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -1047,7 +1047,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -1057,7 +1057,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

4
passes/cmds/wrapcell.cc
View file

@ -59,7 +59,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
auto beg = it;
while (it != fmt.end() && *it != '}') it++;
if (it == fmt.end()) {
log("Unclosed curly brackets in format string '%s'\n", fmt.c_str());
log("Unclosed curly brackets in format string '%s'\n", fmt);
return {};
}
@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
} else {
auto id = RTLIL::escape_id(std::string(beg, it));
if (!parameters.count(id)) {
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt);
return {};
}

4
passes/fsm/fsm_expand.cc
View file

@ -140,7 +140,7 @@ struct FsmExpand
{
optimze_as_needed();
log(" merging %s cell %s.\n", cell->type.c_str(), cell->name.c_str());
log(" merging %s cell %s.\n", cell->type, cell->name);
merged_set.insert(cell);
already_optimized = false;
@ -243,7 +243,7 @@ struct FsmExpand
void execute()
{
log("\n");
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name);
already_optimized = false;
limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();

2
passes/fsm/fsm_export.cc
View file

@ -76,7 +76,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
if (!kiss_file.is_open()) {
log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
log_error("Could not open file \"%s\" with write access.\n", kiss_name);
}
fsm_data.copy_from_cell(cell);

6
passes/fsm/fsm_extract.cc
View file

@ -71,7 +71,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name);
return false;
}
@ -255,7 +255,7 @@ undef_bit_in_next_state:
static void extract_fsm(RTLIL::Wire *wire)
{
log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name);
// get input and output signals for state ff
@ -274,7 +274,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
log(" found %s cell for state register: %s\n", cell->type, cell->name);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
clk = cell->getPort(ID::CLK);

2
passes/fsm/fsm_map.cc
View file

@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name.c_str(), module->name.c_str());
log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name, module->name);
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);

2
passes/fsm/fsm_opt.cc
View file

@ -293,7 +293,7 @@ struct FsmOpt
FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module)
{
log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str());
log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name);
fsm_data.copy_from_cell(cell);
this->cell = cell;

16
passes/fsm/fsm_recode.cc
View file

@ -56,15 +56,15 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
{
std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding);
if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
log(" unknown encoding `%s': using auto instead.\n", encoding.c_str());
log(" unknown encoding `%s': using auto instead.\n", encoding);
encoding = "auto";
}
if (encoding == "none" || encoding == "user") {
log(" nothing to do for encoding `%s'.\n", encoding.c_str());
log(" nothing to do for encoding `%s'.\n", encoding);
return;
}
@ -79,7 +79,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
encoding = default_encoding;
else
encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary";
log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str());
log(" mapping auto encoding to `%s` for this FSM.\n", encoding);
}
if (encoding == "one-hot") {
@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
}
fsm_data.state_bits = new_num_state_bits;
} else
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
log_error("FSM encoding `%s' is not supported!\n", encoding);
if (encfile)
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
@ -113,7 +113,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
} else
log_abort();
log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
log(" %s -> %s\n", fsm_data.state_table[i].as_string(), new_code.as_string());
if (encfile)
fprintf(encfile, ".map %s %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
fsm_data.state_table[i] = new_code;
@ -165,13 +165,13 @@ struct FsmRecodePass : public Pass {
if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
fm_set_fsm_file = fopen(args[++argidx].c_str(), "w");
if (fm_set_fsm_file == NULL)
log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx], strerror(errno));
continue;
}
if (arg == "-encfile" && argidx+1 < args.size() && encfile == NULL) {
encfile = fopen(args[++argidx].c_str(), "w");
if (encfile == NULL)
log_error("Can't open encfile `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
log_error("Can't open encfile `%s' for writing: %s\n", args[argidx], strerror(errno));
continue;
}
if (arg == "-encoding" && argidx+1 < args.size() && default_encoding.empty()) {

2
passes/fsm/fsmdata.h
View file

@ -134,7 +134,7 @@ struct FsmData
{
log("-------------------------------------\n");
log("\n");
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
log(" Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string());
log("\n");
log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs);

12
passes/hierarchy/hierarchy.cc
View file

@ -59,7 +59,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
std::set<RTLIL::IdString> portnames;
std::set<RTLIL::IdString> parameters;
std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
log("Generate module for cell type %s:\n", celltype);
for (auto mod : design->modules())
for (auto cell : mod->cells())
@ -605,9 +605,9 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
return;
if (indent == 0)
log("Top module: %s\n", mod->name.c_str());
log("Top module: %s\n", mod->name);
else if (!mod->get_blackbox_attribute())
log("Used module: %*s%s\n", indent, "", mod->name.c_str());
log("Used module: %*s%s\n", indent, "", mod->name);
used.insert(mod);
for (auto cell : mod->cells()) {
@ -647,7 +647,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
for (auto mod : del_modules) {
if (!purge_lib && mod->get_blackbox_attribute())
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
log("Removing unused module `%s'.\n", mod->name);
design->remove(mod);
del_counter++;
}
@ -873,11 +873,11 @@ struct HierarchyPass : public Pass {
log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
if (decl.index >= 1)
log(" [at position %d]", decl.index);
log(" %s\n", decl.portname.c_str());
log(" %s\n", decl.portname);
generate_ports.push_back(decl);
continue;
is_celltype:
log("Celltype: %s\n", args[argidx].c_str());
log("Celltype: %s\n", args[argidx]);
generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
}
continue;

16
passes/hierarchy/submod.cc
View file

@ -87,7 +87,7 @@ struct SubmodWorker
void handle_submodule(SubModule &submod)
{
log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name);
wire_flags.clear();
for (RTLIL::Cell *cell : submod.cells) {
@ -192,13 +192,13 @@ struct SubmodWorker
}
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: inout %s\n", wire->name, new_wire->name);
else if (new_wire->port_input)
log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: input %s\n", wire->name, new_wire->name);
else if (new_wire->port_output)
log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: output %s\n", wire->name, new_wire->name);
else
log(" signal %s: internal\n", wire->name.c_str());
log(" signal %s: internal\n", wire->name);
flags.new_wire = new_wire;
}
@ -214,7 +214,7 @@ struct SubmodWorker
log_assert(wire_flags.count(bit.wire) > 0);
bit.wire = wire_flags.at(bit.wire).new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
log(" cell %s (%s)\n", new_cell->name, new_cell->type);
if (!copy_mode)
module->remove(cell);
}
@ -250,12 +250,12 @@ struct SubmodWorker
return;
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}
if (module->memories.size() > 0) {
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name);
return;
}

124
passes/memory/memlib.cc
View file

@ -134,7 +134,7 @@ struct Parser {
rewrite_filename(filename);
infile.open(filename);
if (infile.fail()) {
log_error("failed to open %s\n", filename.c_str());
log_error("failed to open %s\n", filename);
}
parse();
infile.close();
@ -181,14 +181,14 @@ struct Parser {
void eat_token(std::string expected) {
std::string token = get_token();
if (token != expected) {
log_error("%s:%d: expected `%s`, got `%s`.\n", filename.c_str(), line_number, expected.c_str(), token.c_str());
log_error("%s:%d: expected `%s`, got `%s`.\n", filename, line_number, expected, token);
}
}
IdString get_id() {
std::string token = get_token();
if (token.empty() || (token[0] != '$' && token[0] != '\\')) {
log_error("%s:%d: expected id string, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected id string, got `%s`.\n", filename, line_number, token);
}
return IdString(token);
}
@ -203,14 +203,14 @@ struct Parser {
if (!isalnum(c) && c != '_')
valid = false;
if (!valid)
log_error("%s:%d: expected name, got `%s`.\n", filename.c_str(), line_number, res.c_str());
log_error("%s:%d: expected name, got `%s`.\n", filename, line_number, res);
return res;
}
std::string get_string() {
std::string token = get_token();
if (token.size() < 2 || token[0] != '"' || token[token.size()-1] != '"') {
log_error("%s:%d: expected string, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected string, got `%s`.\n", filename, line_number, token);
}
return token.substr(1, token.size()-2);
}
@ -225,7 +225,7 @@ struct Parser {
char *endptr;
long res = strtol(token.c_str(), &endptr, 0);
if (token.empty() || *endptr || res > INT_MAX) {
log_error("%s:%d: expected int, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected int, got `%s`.\n", filename, line_number, token);
}
return res;
}
@ -235,7 +235,7 @@ struct Parser {
char *endptr;
double res = strtod(token.c_str(), &endptr);
if (token.empty() || *endptr) {
log_error("%s:%d: expected float, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected float, got `%s`.\n", filename, line_number, token);
}
return res;
}
@ -248,7 +248,7 @@ struct Parser {
void get_semi() {
std::string token = get_token();
if (token != ";") {
log_error("%s:%d: expected `;`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `;`, got `%s`.\n", filename, line_number, token);
}
}
@ -387,7 +387,7 @@ struct Parser {
exit_portoption();
} else if (token == "clock") {
if (port.kind == PortKind::Ar) {
log_error("%s:%d: `clock` not allowed in async read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `clock` not allowed in async read port.\n", filename, line_number);
}
ClockDef def;
token = get_token();
@ -398,7 +398,7 @@ struct Parser {
} else if (token == "negedge") {
def.kind = ClkPolKind::Negedge;
} else {
log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename, line_number, token);
}
if (peek_string()) {
def.name = get_string();
@ -407,13 +407,13 @@ struct Parser {
add_cap(port.clock, def);
} else if (token == "clken") {
if (port.kind == PortKind::Ar) {
log_error("%s:%d: `clken` not allowed in async read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `clken` not allowed in async read port.\n", filename, line_number);
}
get_semi();
add_cap(port.clken, {});
} else if (token == "wrbe_separate") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) {
log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename, line_number);
}
get_semi();
add_cap(port.wrbe_separate, {});
@ -424,14 +424,14 @@ struct Parser {
if (token == "tied") {
get_token();
if (!is_rw)
log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename, line_number);
while (peek_int())
def.wr_widths.push_back(get_int());
def.tied = true;
} else if (token == "mix") {
get_token();
if (!is_rw)
log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename, line_number);
while (peek_int())
def.wr_widths.push_back(get_int());
def.rd_widths = def.wr_widths;
@ -439,7 +439,7 @@ struct Parser {
} else if (token == "rd") {
get_token();
if (!is_rw)
log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename, line_number);
do {
def.rd_widths.push_back(get_int());
} while (peek_int());
@ -451,7 +451,7 @@ struct Parser {
} else if (token == "wr") {
get_token();
if (!is_rw)
log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename, line_number);
do {
def.wr_widths.push_back(get_int());
} while (peek_int());
@ -470,12 +470,12 @@ struct Parser {
add_cap(port.width, def);
} else if (token == "rden") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename, line_number);
get_semi();
add_cap(port.rden, {});
} else if (token == "rdwr") {
if (port.kind != PortKind::Srsw)
log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename, line_number);
RdWrKind kind;
token = get_token();
if (token == "undefined") {
@ -489,13 +489,13 @@ struct Parser {
} else if (token == "new_only") {
kind = RdWrKind::NewOnly;
} else {
log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdwr, kind);
} else if (token == "rdinit") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
ResetValKind kind;
token = get_token();
if (token == "none") {
@ -507,13 +507,13 @@ struct Parser {
} else if (token == "no_undef") {
kind = ResetValKind::NoUndef;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdinit, kind);
} else if (token == "rdarst") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
ResetValKind kind;
token = get_token();
if (token == "none") {
@ -527,13 +527,13 @@ struct Parser {
} else if (token == "init") {
kind = ResetValKind::Init;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.rdarst, kind);
} else if (token == "rdsrst") {
if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw)
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token);
SrstDef def;
token = get_token();
if (token == "none") {
@ -547,7 +547,7 @@ struct Parser {
} else if (token == "init") {
def.val = ResetValKind::Init;
} else {
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token);
}
if (def.val == ResetValKind::None) {
def.kind = SrstKind::None;
@ -560,7 +560,7 @@ struct Parser {
} else if (token == "gated_rden") {
def.kind = SrstKind::GatedRdEn;
} else {
log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename, line_number, token);
}
}
def.block_wr = false;
@ -572,14 +572,14 @@ struct Parser {
add_cap(port.rdsrst, def);
} else if (token == "wrprio") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr)
log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename, line_number);
do {
add_cap(port.wrprio, get_string());
} while (peek_string());
get_semi();
} else if (token == "wrtrans") {
if (port.kind == PortKind::Ar || port.kind == PortKind::Sr)
log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename.c_str(), line_number);
log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename, line_number);
token = peek_token();
RawWrTransDef def;
if (token == "all") {
@ -595,7 +595,7 @@ struct Parser {
} else if (token == "old") {
def.kind = WrTransKind::Old;
} else {
log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(port.wrtrans, def);
@ -609,9 +609,9 @@ struct Parser {
get_semi();
add_cap(port.optional_rw, {});
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing port item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing port item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown port-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown port-level item `%s`.\n", filename, line_number, token);
}
}
@ -646,14 +646,14 @@ struct Parser {
} else if (token == "abits") {
int val = get_int();
if (val < 0)
log_error("%s:%d: abits %d nagative.\n", filename.c_str(), line_number, val);
log_error("%s:%d: abits %d nagative.\n", filename, line_number, val);
get_semi();
add_cap(ram.abits, val);
} else if (token == "width") {
WidthsDef def;
int w = get_int();
if (w <= 0)
log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w);
log_error("%s:%d: width %d not positive.\n", filename, line_number, w);
def.widths.push_back(w);
def.mode = WidthMode::Single;
get_semi();
@ -664,9 +664,9 @@ struct Parser {
do {
int w = get_int();
if (w <= 0)
log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w);
log_error("%s:%d: width %d not positive.\n", filename, line_number, w);
if (w < last * 2)
log_error("%s:%d: width %d smaller than %d required for progression.\n", filename.c_str(), line_number, w, last * 2);
log_error("%s:%d: width %d smaller than %d required for progression.\n", filename, line_number, w, last * 2);
last = w;
def.widths.push_back(w);
} while(peek_int());
@ -676,7 +676,7 @@ struct Parser {
} else if (token == "per_port") {
def.mode = WidthMode::PerPort;
} else {
log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(ram.widths, def);
@ -702,7 +702,7 @@ struct Parser {
} else if (token == "byte") {
int val = get_int();
if (val <= 0)
log_error("%s:%d: byte width %d not positive.\n", filename.c_str(), line_number, val);
log_error("%s:%d: byte width %d not positive.\n", filename, line_number, val);
add_cap(ram.byte, val);
get_semi();
} else if (token == "init") {
@ -717,7 +717,7 @@ struct Parser {
} else if (token == "none") {
kind = MemoryInitKind::None;
} else {
log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename, line_number, token);
}
get_semi();
add_cap(ram.init, kind);
@ -743,7 +743,7 @@ struct Parser {
} else if (token == "srsw") {
port.kind = PortKind::Srsw;
} else {
log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename, line_number, token);
}
do {
port.names.push_back(get_string());
@ -752,9 +752,9 @@ struct Parser {
if (active)
add_cap(ram.ports, port);
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown ram-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown ram-level item `%s`.\n", filename, line_number, token);
}
}
@ -787,7 +787,7 @@ struct Parser {
} else if (token == "huge") {
ram.kind = RamKind::Huge;
} else {
log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename, line_number, token);
}
ram.id = get_id();
parse_ram_block();
@ -795,9 +795,9 @@ struct Parser {
compile_ram(orig_line);
}
} else if (token == "") {
log_error("%s:%d: unexpected EOF while parsing top item.\n", filename.c_str(), line_number);
log_error("%s:%d: unexpected EOF while parsing top item.\n", filename, line_number);
} else {
log_error("%s:%d: unknown top-level item `%s`.\n", filename.c_str(), line_number, token.c_str());
log_error("%s:%d: unknown top-level item `%s`.\n", filename, line_number, token);
}
}
@ -816,7 +816,7 @@ struct Parser {
if (!opts_ok(cap.portopts, portopts))
continue;
if (res)
log_error("%s:%d: duplicate %s cap.\n", filename.c_str(), line_number, name);
log_error("%s:%d: duplicate %s cap.\n", filename, line_number, name);
res = &cap.val;
}
return res;
@ -860,7 +860,7 @@ struct Parser {
} else {
const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock");
if (!cdef)
log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line);
log_error("%s:%d: missing clock capability.\n", filename, orig_line);
var.clk_pol = cdef->kind;
if (cdef->name.empty()) {
var.clk_shared = -1;
@ -876,7 +876,7 @@ struct Parser {
} else {
var.clk_shared = it->second;
if (cram.shared_clocks[var.clk_shared].anyedge != anyedge) {
log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename.c_str(), orig_line, cdef->name.c_str());
log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename, orig_line, cdef->name);
}
}
}
@ -885,7 +885,7 @@ struct Parser {
const PortWidthDef *wdef = find_single_cap(pdef.width, cram.options, portopts, "width");
if (wdef) {
if (cram.width_mode != WidthMode::PerPort)
log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename.c_str(), orig_line);
log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename, orig_line);
compile_widths(var, cram.dbits, *wdef);
} else {
var.width_tied = true;
@ -908,9 +908,9 @@ struct Parser {
var.rdsrstmode = srv->kind;
var.rdsrst_block_wr = srv->block_wr;
if (srv->kind == SrstKind::GatedClkEn && !var.clk_en)
log_error("%s:%d: `gated_clken` used without `clken`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `gated_clken` used without `clken`.\n", filename, orig_line);
if (srv->kind == SrstKind::GatedRdEn && !var.rd_en)
log_error("%s:%d: `gated_rden` used without `rden`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `gated_rden` used without `rden`.\n", filename, orig_line);
} else {
var.rdsrstval = ResetValKind::None;
var.rdsrstmode = SrstKind::None;
@ -918,13 +918,13 @@ struct Parser {
}
if (var.rdarstval == ResetValKind::Init || var.rdsrstval == ResetValKind::Init) {
if (var.rdinitval != ResetValKind::Any && var.rdinitval != ResetValKind::NoUndef) {
log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename.c_str(), orig_line);
log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename, orig_line);
}
}
}
var.wrbe_separate = find_single_cap(pdef.wrbe_separate, cram.options, portopts, "wrbe_separate");
if (var.wrbe_separate && cram.byte == 0) {
log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename.c_str(), orig_line);
log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename, orig_line);
}
for (auto &def: pdef.wrprio) {
if (!opts_ok(def.opts, cram.options))
@ -948,18 +948,18 @@ struct Parser {
grp.variants.push_back(var);
}
if (grp.variants.empty()) {
log_error("%s:%d: all port option combinations are forbidden.\n", filename.c_str(), orig_line);
log_error("%s:%d: all port option combinations are forbidden.\n", filename, orig_line);
}
cram.port_groups.push_back(grp);
}
void compile_ram(int orig_line) {
if (ram.abits.empty())
log_error("%s:%d: `dims` capability should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: `dims` capability should be specified.\n", filename, orig_line);
if (ram.widths.empty())
log_error("%s:%d: `widths` capability should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: `widths` capability should be specified.\n", filename, orig_line);
if (ram.ports.empty())
log_error("%s:%d: at least one port group should be specified.\n", filename.c_str(), orig_line);
log_error("%s:%d: at least one port group should be specified.\n", filename, orig_line);
for (auto opts: make_opt_combinations(ram.opts)) {
bool forbidden = false;
for (auto &fdef: ram.forbid) {
@ -1003,7 +1003,7 @@ struct Parser {
const int *byte = find_single_cap(ram.byte, opts, Options(), "byte");
cram.byte = byte ? *byte : 0;
if (GetSize(cram.dbits) - 1 > cram.abits)
log_error("%s:%d: abits %d too small for dbits progression.\n", filename.c_str(), line_number, cram.abits);
log_error("%s:%d: abits %d too small for dbits progression.\n", filename, line_number, cram.abits);
validate_byte(widths->widths, cram.byte);
const MemoryInitKind *ik = find_single_cap(ram.init, opts, Options(), "init");
cram.init = ik ? *ik : MemoryInitKind::None;
@ -1037,18 +1037,18 @@ struct Parser {
if (widths[0] % byte == 0) {
for (int j = 1; j < GetSize(widths); j++)
if (widths[j] % byte != 0)
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte);
return;
}
for (int i = 0; i < GetSize(widths); i++) {
if (widths[i] == byte) {
for (int j = i + 1; j < GetSize(widths); j++)
if (widths[j] % byte != 0)
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte);
return;
}
}
log_error("%s:%d: byte width %d invalid for dbits.\n", filename.c_str(), line_number, byte);
log_error("%s:%d: byte width %d invalid for dbits.\n", filename, line_number, byte);
}
void compile_widths(PortVariant &var, const std::vector<int> &widths, const PortWidthDef &width) {
@ -1073,13 +1073,13 @@ struct Parser {
if (dbits[i] == widths[0]) {
for (int j = 0; j < GetSize(widths); j++) {
if (i+j >= GetSize(dbits) || dbits[i+j] != widths[j]) {
log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename.c_str(), line_number, widths[j]);
log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename, line_number, widths[j]);
}
}
return {i, i + GetSize(widths) - 1};
}
}
log_error("%s:%d: port width %d invalid for dbits.\n", filename.c_str(), line_number, widths[0]);
log_error("%s:%d: port width %d invalid for dbits.\n", filename, line_number, widths[0]);
}
void parse() {

4
passes/memory/memory_bram.cc
View file

@ -369,7 +369,7 @@ struct rules_t
attr_icase = false;
if (infile.fail())
log_error("Can't open rules file `%s'.\n", filename.c_str());
log_error("Can't open rules file `%s'.\n", filename);
while (next_line())
{
@ -1020,7 +1020,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals)
log(" Properties:");
for (auto &it : match_properties)
log(" %s=%d", it.first.c_str(), it.second);
log(" %s=%d", it.first, it.second);
log("\n");
pool<pair<IdString, int>> failed_brams;

4
passes/memory/memory_dff.cc
View file

@ -334,7 +334,7 @@ struct MemoryDffWorker
void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx)
{
auto &port = mem.rd_ports[idx];
log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, module->name);
std::vector<MuxData> muxdata;
SigSpec data = walk_muxes(port.data, muxdata);
@ -554,7 +554,7 @@ struct MemoryDffWorker
void handle_rd_port_addr(Mem &mem, int idx)
{
auto &port = mem.rd_ports[idx];
log("Checking read port address `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str());
log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, module->name);
FfData ff;
pool<std::pair<Cell *, int>> bits;

10
passes/memory/memory_libmap.cc
View file

@ -548,20 +548,20 @@ void MemMapping::determine_style() {
// Nothing.
} else if (val_s == "logic" || val_s == "registers") {
kind = RamKind::Logic;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "distributed") {
kind = RamKind::Distributed;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") {
kind = RamKind::Block;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else if (val_s == "huge" || val_s == "ultra") {
kind = RamKind::Huge;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid));
log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid));
} else {
kind = RamKind::NotLogic;
style = val_s;
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid), val_s.c_str());
log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s);
}
return;
}

2
passes/memory/memory_map.cc
View file

@ -192,7 +192,7 @@ struct MemoryMapWorker
}
}
log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str());
log("Mapping memory %s in module %s:\n", mem.memid, module->name);
int abits = ceil_log2(mem.size);
std::vector<RTLIL::SigSpec> data_reg_in(1 << abits);

4
passes/memory/memory_share.cc
View file

@ -371,9 +371,9 @@ struct MemoryShareWorker
ports += std::to_string(idx);
}
if (!some_port.clk_enable) {
log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str());
log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports);
} else {
log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str());
log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports);
}
// Okay, time to actually run the SAT solver.

2
passes/opt/opt_clean.cc
View file

@ -597,7 +597,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit)
{
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
log("Finding unused cells or wires in module %s..\n", module->name);
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())

2
passes/opt/opt_lut.cc
View file

@ -99,7 +99,7 @@ struct OptLutWorker
}
for (int i = 0; i < GetSize(dlogic); i++)
{
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]);
log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]);
}
}

2
passes/opt/opt_merge.cc
View file

@ -228,7 +228,7 @@ struct OptMergeWorker
ct.cell_types.erase(ID($allseq));
ct.cell_types.erase(ID($allconst));
log("Finding identical cells in module `%s'.\n", module->name.c_str());
log("Finding identical cells in module `%s'.\n", module->name);
assign_map.set(module);
initvals.set(&assign_map, module);

2
passes/opt/opt_muxtree.cc
View file

@ -205,7 +205,7 @@ struct OptMuxtreeWorker
OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) :
design(design), module(module), assign_map(module), removed_count(0)
{
log("Running muxtree optimizer on module %s..\n", module->name.c_str());
log("Running muxtree optimizer on module %s..\n", module->name);
log(" Creating internal representation of mux trees.\n");

14
passes/opt/opt_reduce.cc
View file

@ -93,7 +93,7 @@ struct OptReduceWorker
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
did_something = true;
total_count++;
}
@ -155,7 +155,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::B, new_sig_b);
@ -242,7 +242,7 @@ struct OptReduceWorker
}
if (new_sig_s.size() != sig_s.size()) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::A, new_sig_a);
@ -308,7 +308,7 @@ struct OptReduceWorker
if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0)
return;
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
@ -388,7 +388,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
@ -479,7 +479,7 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
@ -515,7 +515,7 @@ struct OptReduceWorker
OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) :
design(design), module(module), assign_map(module)
{
log(" Optimizing cells in module %s.\n", module->name.c_str());
log(" Optimizing cells in module %s.\n", module->name);
total_count = 0;
did_something = true;

10
passes/opt/rmports.cc
View file

@ -64,7 +64,7 @@ struct RmportsPassPass : public Pass {
void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Removing now-unused cell ports in module %s\n", module->name.c_str());
log("Removing now-unused cell ports in module %s\n", module->name);
auto cells = module->cells();
for(auto cell : cells)
@ -88,7 +88,7 @@ struct RmportsPassPass : public Pass {
void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Finding unconnected ports in module %s\n", module->name.c_str());
log("Finding unconnected ports in module %s\n", module->name);
pool<IdString> used_ports;
@ -113,7 +113,7 @@ struct RmportsPassPass : public Pass {
if( (w1 == NULL) || (w2 == NULL) )
continue;
//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());
//log(" conn %s, %s\n", w1->name, w2->name);
if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
used_ports.insert(w1->name);
@ -136,7 +136,7 @@ struct RmportsPassPass : public Pass {
if(sig == NULL)
continue;
// log(" sig %s\n", sig->name.c_str());
// log(" sig %s\n", sig->name);
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
used_ports.insert(sig->name);
}
@ -155,7 +155,7 @@ struct RmportsPassPass : public Pass {
// Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused port %s\n", port.c_str());
log(" removing unused port %s\n", port);
removed_ports[module->name].insert(port);
// Remove from ports list

4
passes/pmgen/pmgen.py
View file

@ -454,7 +454,7 @@ with open(outfile, "w") as f:
print(" SigSpec port(Cell *cell, IdString portname) {", file=f)
print(" try {", file=f)
print(" return sigmap(cell->getPort(portname));", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname.c_str()); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f)
@ -465,7 +465,7 @@ with open(outfile, "w") as f:
print(" Const param(Cell *cell, IdString paramname) {", file=f)
print(" try {", file=f)
print(" return cell->getParam(paramname);", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname.c_str()); }", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f)

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