From e0ae7b7af44a45795f68990cd16a85bf03770d2a Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 11 Sep 2025 05:25:26 +0000 Subject: [PATCH] Remove .c_str() calls from log()/log_error() There are some leftovers, but this is an easy regex-based approach that removes most of them. --- backends/aiger/aiger.cc | 4 +- backends/aiger/xaiger.cc | 2 +- backends/blif/blif.cc | 2 +- backends/btor/btor.cc | 4 +- backends/edif/edif.cc | 2 +- backends/firrtl/firrtl.cc | 6 +- backends/functional/cxx.cc | 2 +- backends/functional/smtlib.cc | 2 +- backends/functional/smtlib_rosette.cc | 2 +- backends/functional/test_generic.cc | 2 +- backends/intersynth/intersynth.cc | 4 +- backends/jny/jny.cc | 4 +- backends/json/json.cc | 4 +- backends/rtlil/rtlil_backend.cc | 6 +- backends/simplec/simplec.cc | 14 +- backends/smt2/smt2.cc | 8 +- backends/smv/smv.cc | 4 +- backends/spice/spice.cc | 2 +- backends/verilog/verilog_backend.cc | 6 +- .../source/code_examples/extensions/my_cmd.cc | 2 +- docs/source/code_examples/functional/dummy.cc | 2 +- docs/source/yosys_internals/hashing.rst | 6 +- examples/cxx-api/scopeinfo_example.cc | 4 +- frontends/aiger/aigerparse.cc | 2 +- frontends/aiger2/xaiger.cc | 4 +- frontends/ast/ast.cc | 24 ++-- frontends/ast/dpicall.cc | 20 +-- frontends/ast/genrtlil.cc | 2 +- frontends/ast/simplify.cc | 26 ++-- frontends/blif/blifparse.cc | 2 +- frontends/json/jsonparse.cc | 4 +- frontends/liberty/liberty.cc | 12 +- frontends/rpc/rpc_frontend.cc | 20 +-- frontends/rtlil/rtlil_frontend.cc | 2 +- frontends/verific/verific.cc | 24 ++-- frontends/verific/verificsva.cc | 2 +- frontends/verilog/preproc.cc | 8 +- frontends/verilog/verilog_frontend.cc | 2 +- frontends/verilog/verilog_parser.y | 6 +- kernel/driver.cc | 10 +- kernel/fstdata.cc | 4 +- kernel/functional.cc | 12 +- kernel/functional.h | 6 +- kernel/gzip.cc | 2 +- kernel/log.cc | 16 +-- kernel/log.h | 2 +- kernel/log_help.cc | 6 +- kernel/register.cc | 64 ++++----- kernel/rtlil.cc | 2 +- kernel/sexpr.cc | 2 +- kernel/tclapi.cc | 2 +- kernel/yosys.cc | 18 +-- kernel/yw.cc | 30 ++--- passes/cmds/abstract.cc | 2 +- passes/cmds/add.cc | 14 +- passes/cmds/cover.cc | 2 +- passes/cmds/edgetypes.cc | 2 +- passes/cmds/exec.cc | 2 +- passes/cmds/glift.cc | 2 +- passes/cmds/internal_stats.cc | 8 +- passes/cmds/linecoverage.cc | 4 +- passes/cmds/logcmd.cc | 2 +- passes/cmds/logger.cc | 8 +- passes/cmds/plugin.cc | 6 +- passes/cmds/portarcs.cc | 2 +- passes/cmds/portlist.cc | 2 +- passes/cmds/printattrs.cc | 10 +- passes/cmds/rename.cc | 6 +- passes/cmds/scc.cc | 2 +- passes/cmds/scratchpad.cc | 18 +-- passes/cmds/select.cc | 16 +-- passes/cmds/setundef.cc | 6 +- passes/cmds/show.cc | 12 +- passes/cmds/splice.cc | 2 +- passes/cmds/stat.cc | 74 +++++------ passes/cmds/timeest.cc | 4 +- passes/cmds/viz.cc | 8 +- passes/cmds/wrapcell.cc | 4 +- passes/fsm/fsm_expand.cc | 4 +- passes/fsm/fsm_export.cc | 2 +- passes/fsm/fsm_extract.cc | 6 +- passes/fsm/fsm_map.cc | 2 +- passes/fsm/fsm_opt.cc | 2 +- passes/fsm/fsm_recode.cc | 16 +-- passes/fsm/fsmdata.h | 2 +- passes/hierarchy/hierarchy.cc | 12 +- passes/hierarchy/submod.cc | 16 +-- passes/memory/memlib.cc | 124 +++++++++--------- passes/memory/memory_bram.cc | 4 +- passes/memory/memory_dff.cc | 4 +- passes/memory/memory_libmap.cc | 10 +- passes/memory/memory_map.cc | 2 +- passes/memory/memory_share.cc | 4 +- passes/opt/opt_clean.cc | 2 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_merge.cc | 2 +- passes/opt/opt_muxtree.cc | 2 +- passes/opt/opt_reduce.cc | 14 +- passes/opt/rmports.cc | 10 +- passes/pmgen/pmgen.py | 4 +- passes/proc/proc_arst.cc | 4 +- passes/proc/proc_clean.cc | 4 +- passes/proc/proc_dff.cc | 6 +- passes/proc/proc_dlatch.cc | 2 +- passes/proc/proc_init.cc | 2 +- passes/proc/proc_mux.cc | 2 +- passes/sat/eval.cc | 32 ++--- passes/sat/fminit.cc | 10 +- passes/sat/freduce.cc | 4 +- passes/sat/mutate.cc | 8 +- passes/sat/qbfsat.cc | 22 ++-- passes/sat/sat.cc | 12 +- passes/sat/sim.cc | 60 ++++----- passes/sat/synthprop.cc | 2 +- passes/techmap/abc.cc | 42 +++--- passes/techmap/abc9.cc | 6 +- passes/techmap/abc9_exe.cc | 14 +- passes/techmap/abc9_ops.cc | 4 +- passes/techmap/attrmap.cc | 4 +- passes/techmap/clkbufmap.cc | 4 +- passes/techmap/clockgate.cc | 6 +- passes/techmap/dfflegalize.cc | 6 +- passes/techmap/dfflibmap.cc | 10 +- passes/techmap/extract.cc | 16 +-- passes/techmap/extract_counter.cc | 6 +- passes/techmap/extract_reduce.cc | 4 +- passes/techmap/extractinv.cc | 2 +- passes/techmap/flowmap.cc | 2 +- passes/techmap/iopadmap.cc | 6 +- passes/techmap/libcache.cc | 4 +- passes/techmap/libparse.cc | 6 +- passes/techmap/libparse.h | 2 +- passes/techmap/techmap.cc | 10 +- passes/tests/raise_error.cc | 2 +- passes/tests/test_autotb.cc | 2 +- passes/tests/test_cell.cc | 2 +- techlibs/coolrunner2/coolrunner2_fixup.cc | 14 +- techlibs/ice40/ice40_braminit.cc | 4 +- techlibs/microchip/microchip_dffopt.cc | 2 +- techlibs/xilinx/xilinx_dffopt.cc | 2 +- 140 files changed, 623 insertions(+), 623 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index e8b8e32ce..95f4c19e2 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -1040,7 +1040,7 @@ struct AigerBackend : public Backend { std::ofstream mapf; mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) - log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno)); writer.write_map(mapf, verbose_map, no_startoffset); } @@ -1051,7 +1051,7 @@ struct AigerBackend : public Backend { PrettyJson json; if (!json.write_to_file(yw_map_filename)) - log_error("Can't open file `%s' for writing: %s\n", yw_map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", yw_map_filename, strerror(errno)); writer.write_ywmap(json); } } diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 97dec40e4..988bc558b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -788,7 +788,7 @@ struct XAigerBackend : public Backend { std::ofstream mapf; mapf.open(map_filename.c_str(), std::ofstream::trunc); if (mapf.fail()) - log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", map_filename, strerror(errno)); writer.write_map(mapf); } } diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 1ce1ac955..ab7861802 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -674,7 +674,7 @@ struct BlifBackend : public Backend { } if (!top_module_name.empty()) - log_error("Can't find top module `%s'!\n", top_module_name.c_str()); + log_error("Can't find top module `%s'!\n", top_module_name); for (auto module : mod_list) BlifDumper::dump(*f, module, design, config); diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index c2b831a44..3cbb5defc 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -246,7 +246,7 @@ struct BtorWorker string cell_list; for (auto c : cell_recursion_guard) cell_list += stringf("\n %s", log_id(c)); - log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list.c_str()); + log_error("Found topological loop while processing cell %s. Active cells:%s\n", log_id(cell), cell_list); } cell_recursion_guard.insert(cell); @@ -1489,7 +1489,7 @@ struct BtorWorker std::ofstream f; f.open(info_filename.c_str(), std::ofstream::trunc); if (f.fail()) - log_error("Can't open file `%s' for writing: %s\n", info_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", info_filename, strerror(errno)); for (auto &it : info_lines) f << it; f.close(); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index cda017059..83d0afaf3 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -519,7 +519,7 @@ struct EdifBackend : public Backend { continue; } else { for (auto &ref : it.second) - log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first.c_str()); + log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.first); log_abort(); } } diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index cda3d4618..e54b46e63 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -347,7 +347,7 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f) auto modInstance = design->module(cell->type); // Ensure that we actually have a module instance if (modInstance == nullptr) { - log_error("Unknown cell type %s\n", cell->type.c_str()); + log_error("Unknown cell type %s\n", cell->type); return; } @@ -505,14 +505,14 @@ struct FirrtlWorker sinkExpr = firstName; break; default: - log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir); + log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type, log_signal(it->second), dir); break; } // Check for subfield assignment. std::string bitsString = "bits("; if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) { if (sinkSig == nullptr) - log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str()); + log_error("Unknown subfield %s.%s\n", cell_type, sinkExpr); // Don't generate the assignment here. // Add the source and sink to the "reverse_wire_map" and we'll output the assignment // as part of the coalesced subfield assignments for this wire. diff --git a/backends/functional/cxx.cc b/backends/functional/cxx.cc index 1f677120a..7f4ad1ea7 100644 --- a/backends/functional/cxx.cc +++ b/backends/functional/cxx.cc @@ -268,7 +268,7 @@ struct FunctionalCxxBackend : public Backend extra_args(f, filename, args, argidx, design); for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); printCxx(*f, filename, module); } } diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 3eacf407c..1504c8fba 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -285,7 +285,7 @@ struct FunctionalSmtBackend : public Backend { extra_args(f, filename, args, argidx, design); for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); SmtModule smt(module); smt.write(*f); } diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index c9e737d19..8abfe3e41 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -307,7 +307,7 @@ struct FunctionalSmtrBackend : public Backend { } for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); SmtrModule smtr(module); smtr.write(*f); } diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 42d6c2b95..a0474ea2b 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -143,7 +143,7 @@ struct FunctionalTestGeneric : public Pass */ for (auto module : design->selected_modules()) { - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); auto fir = Functional::IR::from_module(module); for(auto node : fir) std::cout << RTLIL::unescape_id(node.name()) << " = " << node.to_string([](auto n) { return RTLIL::unescape_id(n.name()); }) << "\n"; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 4c098e019..78eab17da 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -100,13 +100,13 @@ struct IntersynthBackend : public Backend { } extra_args(f, filename, args, argidx); - log("Output filename: %s\n", filename.c_str()); + log("Output filename: %s\n", filename); for (auto filename : libfiles) { std::ifstream f; f.open(filename.c_str()); if (f.fail()) - log_error("Can't open lib file `%s'.\n", filename.c_str()); + log_error("Can't open lib file `%s'.\n", filename); RTLIL::Design *lib = new RTLIL::Design; Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 001492e40..ee0c0d14c 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -553,7 +553,7 @@ struct JnyPass : public Pass { ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; invk << filename; @@ -568,7 +568,7 @@ struct JnyPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } diff --git a/backends/json/json.cc b/backends/json/json.cc index f7b80d53d..b04083622 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -701,7 +701,7 @@ struct JsonPass : public Pass { ff->open(filename.c_str(), std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } else { @@ -714,7 +714,7 @@ struct JsonPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } } JsonPass; diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 215e0d366..cb17432b1 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -458,7 +458,7 @@ struct RTLILBackend : public Backend { design->sort(); - log("Output filename: %s\n", filename.c_str()); + log("Output filename: %s\n", filename); *f << stringf("# Generated by %s\n", yosys_maybe_version()); RTLIL_BACKEND::dump_design(*f, design, selected, true, false); @@ -531,7 +531,7 @@ struct DumpPass : public Pass { ff->open(filename.c_str(), append ? std::ofstream::app : std::ofstream::trunc); if (ff->fail()) { delete ff; - log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } else { @@ -543,7 +543,7 @@ struct DumpPass : public Pass { if (!empty) { delete f; } else { - log("%s", buf.str().c_str()); + log("%s", buf.str()); } } } DumpPass; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 1ab586e43..ed981f961 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -504,7 +504,7 @@ struct SimplecWorker while (work->dirty) { if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty())) - log(" In %s:\n", work->log_prefix.c_str()); + log(" In %s:\n", work->log_prefix); while (!work->dirty_bits.empty() || !work->dirty_cells.empty()) { @@ -517,7 +517,7 @@ struct SimplecWorker if (chunk.wire == nullptr) continue; if (verbose) - log(" Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset); + log(" Propagating %s.%s[%d:%d].\n", work->log_prefix, log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset); funct_declarations.push_back(stringf(" // Updated signal in %s: %s", work->log_prefix, log_signal(chunk))); } @@ -539,7 +539,7 @@ struct SimplecWorker work->parent->set_dirty(parent_bit); if (verbose) - log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset, + log(" Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset, work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset); } @@ -556,11 +556,11 @@ struct SimplecWorker child->set_dirty(child_bit); if (verbose) - log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset, + log(" Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix, log_id(bit.wire), bit.offset, work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset); } else { if (verbose) - log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)), + log(" Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix, log_id(std::get<0>(port)), work->log_prefix.c_str(), log_id(bit.wire), bit.offset); work->set_dirty(std::get<0>(port)); } @@ -579,7 +579,7 @@ struct SimplecWorker string hiername = work->log_prefix + "." + log_id(cell); if (verbose) - log(" Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells)); + log(" Evaluating %s (%s, best of %d).\n", hiername, log_id(cell->type), GetSize(work->dirty_cells)); if (activated_cells.count(hiername)) reactivated_cells.insert(hiername); @@ -630,7 +630,7 @@ struct SimplecWorker void make_func(HierDirtyFlags *work, const string &func_name, const vector &preamble) { - log("Generating function %s():\n", func_name.c_str()); + log("Generating function %s():\n", func_name); activated_cells.clear(); reactivated_cells.clear(); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 089e73715..1d3757463 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -130,7 +130,7 @@ struct Smt2Worker for (auto &mem : memories) { if (is_smtlib2_module) - log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid.c_str()); + log_error("Memory %s.%s not allowed in module with smtlib2_module attribute", get_id(module), mem.memid); mem.narrow(); mem_dict[mem.memid] = &mem; @@ -620,11 +620,11 @@ struct Smt2Worker decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(QY)), infostr)); if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::maximize)){ decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str().c_str()); + log("Wire %s is maximized\n", cell->getPort(QY).as_wire()->name.str()); } else if (cell->getPort(QY).is_wire() && cell->getPort(QY).as_wire()->get_bool_attribute(ID::minimize)){ decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter)); - log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str().c_str()); + log("Wire %s is minimized\n", cell->getPort(QY).as_wire()->name.str()); } bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst)); @@ -1776,7 +1776,7 @@ struct Smt2Backend : public Backend { if (args[argidx] == "-tpl" && argidx+1 < args.size()) { template_f.open(args[++argidx]); if (template_f.fail()) - log_error("Can't open template file `%s'.\n", args[argidx].c_str()); + log_error("Can't open template file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-bv" || args[argidx] == "-mem") { diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 55eadca00..a6ccbf27f 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -756,7 +756,7 @@ struct SmvBackend : public Backend { if (args[argidx] == "-tpl" && argidx+1 < args.size()) { template_f.open(args[++argidx]); if (template_f.fail()) - log_error("Can't open template file `%s'.\n", args[argidx].c_str()); + log_error("Can't open template file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-verbose") { @@ -795,7 +795,7 @@ struct SmvBackend : public Backend { modules.erase(module); if (module == nullptr) - log_error("Module '%s' not found.\n", stmt[1].c_str()); + log_error("Module '%s' not found.\n", stmt[1]); *f << stringf("-- SMV description generated by %s\n", yosys_maybe_version()); diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 573093ff7..16458d647 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -258,7 +258,7 @@ struct SpiceBackend : public Backend { if (!top_module_name.empty()) { if (top_module == NULL) - log_error("Can't find top module `%s'!\n", top_module_name.c_str()); + log_error("Can't find top module `%s'!\n", top_module_name); print_spice_module(*f, top_module, design, neg, pos, buf, ncpf, big_endian, use_inames); *f << stringf("\n"); } diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b1ed2b1f0..71969f177 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -153,7 +153,7 @@ void reset_auto_counter(RTLIL::Module *module) if (verbose) for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it) - log(" renaming `%s' to `%s_%0*d_'.\n", it->first.c_str(), auto_prefix.c_str(), auto_name_digits, auto_name_offset + it->second); + log(" renaming `%s' to `%s_%0*d_'.\n", it->first, auto_prefix, auto_name_digits, auto_name_offset + it->second); } std::string next_auto_id() @@ -494,7 +494,7 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem) std::ofstream extmem_f(extmem_filename, std::ofstream::trunc); if (extmem_f.fail()) - log_error("Can't open file `%s' for writing: %s\n", extmem_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", extmem_filename, strerror(errno)); else { Const data = mem.get_init_data(); @@ -2632,7 +2632,7 @@ struct VerilogBackend : public Backend { log_cmd_error("Can't handle partially selected module %s!\n", log_id(module->name)); continue; } - log("Dumping module `%s'.\n", module->name.c_str()); + log("Dumping module `%s'.\n", module->name); module->sort(); dump_module(*f, "", module); } diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc index e6660469c..d52268b4a 100644 --- a/docs/source/code_examples/extensions/my_cmd.cc +++ b/docs/source/code_examples/extensions/my_cmd.cc @@ -10,7 +10,7 @@ struct MyPass : public Pass { { log("Arguments to my_cmd:\n"); for (auto &arg : args) - log(" %s\n", arg.c_str()); + log(" %s\n", arg); log("Modules in current design:\n"); for (auto mod : design->modules()) diff --git a/docs/source/code_examples/functional/dummy.cc b/docs/source/code_examples/functional/dummy.cc index 3d84b84ba..42b05b339 100644 --- a/docs/source/code_examples/functional/dummy.cc +++ b/docs/source/code_examples/functional/dummy.cc @@ -16,7 +16,7 @@ struct FunctionalDummyBackend : public Backend { for (auto module : design->selected_modules()) { - log("Processing module `%s`.\n", module->name.c_str()); + log("Processing module `%s`.\n", module->name); // convert module to FunctionalIR auto ir = Functional::IR::from_module(module); diff --git a/docs/source/yosys_internals/hashing.rst b/docs/source/yosys_internals/hashing.rst index b9608d99e..1993e617a 100644 --- a/docs/source/yosys_internals/hashing.rst +++ b/docs/source/yosys_internals/hashing.rst @@ -45,9 +45,9 @@ creates a bijective map from ``K`` to the integers. For example: log("%d\n", si("world")); // will print 43 log("%d\n", si.at("world")); // will print 43 log("%d\n", si.at("dummy")); // will throw exception - log("%s\n", si[42].c_str())); // will print hello - log("%s\n", si[43].c_str())); // will print world - log("%s\n", si[44].c_str())); // will throw exception + log("%s\n", si[42])); // will print hello + log("%s\n", si[43])); // will print world + log("%s\n", si[44])); // will throw exception It is not possible to remove elements from an idict. diff --git a/examples/cxx-api/scopeinfo_example.cc b/examples/cxx-api/scopeinfo_example.cc index 0882ba804..fd5d2a781 100644 --- a/examples/cxx-api/scopeinfo_example.cc +++ b/examples/cxx-api/scopeinfo_example.cc @@ -77,9 +77,9 @@ struct ScopeinfoExamplePass : public Pass { continue; } - log("%s %s\n", wire_scope.first.path_str().c_str(), log_id(wire_scope.second)); + log("%s %s\n", wire_scope.first.path_str(), log_id(wire_scope.second)); for (auto src : index.sources(wire)) - log(" - %s\n", src.c_str()); + log(" - %s\n", src); } } } diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index c5d9bc70b..db4cb12ba 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -909,7 +909,7 @@ void AigerReader::post_process() module->rename(cell, escaped_s); } else - log_error("Symbol type '%s' not recognised.\n", type.c_str()); + log_error("Symbol type '%s' not recognised.\n", type); } } diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 616bec9e7..d983f8c41 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -91,7 +91,7 @@ struct Xaiger2Frontend : public Frontend { std::ifstream map_file; map_file.open(map_filename); if (!map_file) - log_error("Failed to open map file '%s'\n", map_filename.c_str()); + log_error("Failed to open map file '%s'\n", map_filename); unsigned int M, I, L, O, A; std::string header; @@ -388,7 +388,7 @@ struct Xaiger2Frontend : public Frontend { if (f->eof()) break; log_assert(!f->fail()); - log("input file: %s\n", scratch.c_str()); + log("input file: %s\n", scratch); } log_debug("co_counter=%d\n", co_counter); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 313161fc3..2f93ea198 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1108,9 +1108,9 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); if (defer) - log("Storing AST representation for module `%s'.\n", ast->str.c_str()); + log("Storing AST representation for module `%s'.\n", ast->str); else if (!quiet) { - log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str()); + log("Generating RTLIL representation for module `%s'.\n", ast->str); } AstModule *module = new AstModule; @@ -1411,7 +1411,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump for (auto& n : design->verilog_packages) { for (auto &o : n->children) { auto cloned_node = o->clone(); - // log("cloned node %s\n", type2str(cloned_node->type).c_str()); + // log("cloned node %s\n", type2str(cloned_node->type)); if (cloned_node->type == AST_ENUM) { for (auto &e : cloned_node->children) { log_assert(e->type == AST_ENUM_ITEM); @@ -1432,7 +1432,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump for (const auto& node : child->children) if (node->type == AST_PARAMETER && param_has_no_default(node.get())) { - log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str.c_str()); + log("Deferring `%s' because it contains parameter(s) without defaults.\n", child->str); defer_local = true; break; } @@ -1507,7 +1507,7 @@ std::pair AST::split_modport_from_type(std::string name interface_modport = seglist[1]; } else { // Erroneous port type - log_error("More than two '.' in signal port type (%s)\n", name_type.c_str()); + log_error("More than two '.' in signal port type (%s)\n", name_type); } } return std::pair(interface_type, interface_modport); @@ -1720,7 +1720,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictset_bool_attribute(ID::is_interface); } else { - log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str()); + log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname); } } @@ -1731,7 +1731,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictmodule(modname)->check(); } else if (!quiet) { - log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); + log("Found cached RTLIL representation for module `%s'.\n", modname); } return modname; @@ -1799,14 +1799,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictstr); if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + log("Parameter %s = %s\n", child->str, log_signal(it->second)); named_parameters.emplace_back(child->str, it->second); continue; } it = parameters.find(stringf("$%d", para_counter)); if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second)); named_parameters.emplace_back(child->str, it->second); continue; } @@ -1839,13 +1839,13 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictstr); if (it != parameters.end()) { if (!quiet) - log("Parameter %s = %s\n", child->str.c_str(), log_signal(it->second)); + log("Parameter %s = %s\n", child->str, log_signal(it->second)); goto rewrite_parameter; } it = parameters.find(stringf("$%d", para_counter)); if (it != parameters.end()) { if (!quiet) - log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(it->second)); + log("Parameter %d (%s) = %s\n", para_counter, child->str, log_signal(it->second)); goto rewrite_parameter; } continue; diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index d76318739..4c2a7fac9 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -40,7 +40,7 @@ static ffi_fptr resolve_fn (std::string symbol_name) plugin_name = loaded_plugin_aliases.at(plugin_name); if (loaded_plugins.count(plugin_name) == 0) - log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name.c_str(), plugin_name.c_str()); + log_error("unable to resolve '%s': can't find plugin `%s'\n", symbol_name, plugin_name); void *symbol = dlsym(loaded_plugins.at(plugin_name), real_symbol_name.c_str()); @@ -61,7 +61,7 @@ static ffi_fptr resolve_fn (std::string symbol_name) if (symbol != nullptr) return (ffi_fptr) symbol; - log_error("unable to resolve '%s'.\n", symbol_name.c_str()); + log_error("unable to resolve '%s'.\n", symbol_name); } std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string &rtype, const std::string &fname, const std::vector &argtypes, const std::vector> &args) @@ -74,32 +74,32 @@ std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string ffi_cif cif; int status; - log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str()); + log("Calling DPI function `%s' and returning `%s':\n", fname, rtype); log_assert(GetSize(args) == GetSize(argtypes)); for (int i = 0; i < GetSize(args); i++) { if (argtypes[i] == "real") { - log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed)); + log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed)); value_store[i].f64 = args[i]->asReal(args[i]->is_signed); values[i] = &value_store[i].f64; types[i] = &ffi_type_double; } else if (argtypes[i] == "shortreal") { - log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed)); + log(" arg %d (%s): %f\n", i, argtypes[i], args[i]->asReal(args[i]->is_signed)); value_store[i].f32 = args[i]->asReal(args[i]->is_signed); values[i] = &value_store[i].f32; types[i] = &ffi_type_double; } else if (argtypes[i] == "integer") { - log(" arg %d (%s): %lld\n", i, argtypes[i].c_str(), (long long)args[i]->asInt(args[i]->is_signed)); + log(" arg %d (%s): %lld\n", i, argtypes[i], (long long)args[i]->asInt(args[i]->is_signed)); value_store[i].i32 = args[i]->asInt(args[i]->is_signed); values[i] = &value_store[i].i32; types[i] = &ffi_type_sint32; } else if (argtypes[i] == "chandle") { - log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false)); + log(" arg %d (%s): %llx\n", i, argtypes[i], (unsigned long long)args[i]->asInt(false)); value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed); values[i] = &value_store[i].ptr; types[i] = &ffi_type_pointer; } else { - log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i); + log_error("invalid argtype '%s' for argument %d.\n", argtypes[i], i); } } @@ -116,7 +116,7 @@ std::unique_ptr AST::dpi_call(AstSrcLocType loc, const std::string types[args.size()] = &ffi_type_pointer; values[args.size()] = &value_store[args.size()].ptr; } else { - log_error("invalid rtype '%s'.\n", rtype.c_str()); + log_error("invalid rtype '%s'.\n", rtype); } if ((status = ffi_prep_cif(&cif, FFI_DEFAULT_ABI, args.size(), types[args.size()], types.data())) != FFI_OK) @@ -155,7 +155,7 @@ YOSYS_NAMESPACE_BEGIN std::unique_ptr AST::dpi_call(AstSrcLocType, const std::string&, const std::string &fname, const std::vector&, const std::vector>&) { - log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname.c_str()); + log_error("Can't call DPI function `%s': this version of yosys is built without plugin support\n", fname); } YOSYS_NAMESPACE_END diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 896ae9bdb..a30823e24 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -382,7 +382,7 @@ struct AST_INTERNAL::ProcessGenerator if (found_anyedge_syncs) { if (found_global_syncs) always->input_error("Found non-synthesizable event list!\n"); - log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str()); + log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string()); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bf72a770f..dee4d5854 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -180,10 +180,10 @@ void AstNode::annotateTypedEnums(AstNode *template_node) if (template_node->attributes.count(ID::enum_type)) { //get reference to enum node: std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str(); - // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type)); + // log("enum_type=%s (count=%lu)\n", enum_type, current_scope.count(enum_type)); // log("current scope:\n"); // for (auto &it : current_scope) - // log(" %s\n", it.first.c_str()); + // log(" %s\n", it.first); log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); @@ -911,7 +911,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin #if 0 log("-------------\n"); - log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename->c_str(), location.begin.line, type2str(type).c_str(), this); + log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, location.begin.filename, location.begin.line, type2str(type), this); log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n", int(const_fold), int(stage), int(width_hint), int(sign_hint)); // dumpAst(nullptr, "> "); @@ -963,7 +963,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS)) goto verbose_activate; - // log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags)); + // log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags)); continue; verbose_activate: @@ -978,7 +978,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } silent_activate: - // log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags)); + // log("Note: Replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str, long(memflags)); mem2reg_set.insert(mem); } @@ -1063,7 +1063,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true); if (str.substr(0, 8) == "$display") fmt.append_literal("\n"); - log("%s", fmt.render().c_str()); + log("%s", fmt.render()); } return false; @@ -1499,7 +1499,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin break; case AST_ENUM: - //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); + //log("\nENUM %s: %d child %d\n", str, basic_prep, children[0]->basic_prep); if (!basic_prep) { for (auto& item_node : children) { while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false)) @@ -1590,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin } default: - log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type).c_str()); + log_error("Don't know how to translate static cast of type %s\n", type2str(template_node->type)); } } @@ -2297,7 +2297,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; str = try_pop_module_prefix(); for (auto& node : current_scope_ast->children) { - //log("looking at mod scope child %s\n", type2str(node->type).c_str()); + //log("looking at mod scope child %s\n", type2str(node->type)); switch (node->type) { case AST_PARAMETER: case AST_LOCALPARAM: @@ -2308,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin case AST_FUNCTION: case AST_TASK: case AST_DPI_FUNCTION: - //log("found child %s, %s\n", type2str(node->type).c_str(), node->str.c_str()); + //log("found child %s, %s\n", type2str(node->type), node->str); if (str == node->str) { - //log("add %s, type %s to scope\n", str.c_str(), type2str(node->type).c_str()); + //log("add %s, type %s to scope\n", str, type2str(node->type)); current_scope[node->str] = node.get(); } break; @@ -2319,7 +2319,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin for (auto& enum_node : node->children) { log_assert(enum_node->type==AST_ENUM_ITEM); if (str == enum_node->str) { - //log("\nadding enum item %s to scope\n", str.c_str()); + //log("\nadding enum item %s to scope\n", str); current_scope[str] = enum_node.get(); } } @@ -5404,7 +5404,7 @@ std::unique_ptr AstNode::eval_const_function(AstNode *fcall, bool must_ #if 0 log("-----------------------------------\n"); for (auto &it : variables) - log("%20s %40s\n", it.first.c_str(), log_signal(it.second.val)); + log("%20s %40s\n", it.first, log_signal(it.second.val)); stmt->dumpAst(nullptr, "stmt> "); #endif if (stmt->type == AST_WIRE) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index f6b894563..d63044923 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -618,7 +618,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool error: log_error("Syntax error in line %d!\n", line_count); error_with_reason: - log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str()); + log_error("Syntax error in line %d: %s\n", line_count, err_reason); } struct BlifFrontend : public Frontend { diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 1aab81015..f2faa669b 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -289,7 +289,7 @@ void json_parse_attr_param(dict &results, JsonNode *node) void json_import(Design *design, string &modname, JsonNode *node) { - log("Importing module %s from JSON tree.\n", modname.c_str()); + log("Importing module %s from JSON tree.\n", modname); Module *module = new RTLIL::Module; module->name = RTLIL::escape_id(modname.c_str()); @@ -367,7 +367,7 @@ void json_import(Design *design, string &modname, JsonNode *node) port_wire->port_input = true; port_wire->port_output = true; } else - log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str()); + log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string); port_wire->port_id = port_id; diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 3228f02fb..72ad8b2b7 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& std::string id = RTLIL::escape_id(std::string(expr, id_len)); if (!module->wires_.count(id)) - log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str()); + log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id)); expr += id_len; return module->wires_.at(id); @@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend { if (cell->id != "cell" || cell->args.size() != 1) continue; - // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); + // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name)); std::map> type_map = global_type_map; parse_type_map(type_map, cell); @@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend { { if (!flag_ignore_miss_dir) { - log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name)); + log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name)); } else { - log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str()); + log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0)); delete module; goto skip_cell; } @@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend { if (node->id == "bus" && node->args.size() == 1) { if (flag_ignore_buses) { - log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str()); + log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0)); delete module; goto skip_cell; } @@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend { } if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal")) - log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name)); + log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name)); simple_comb_cell = false; diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 4a9ce4b8a..df64ecd2f 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -167,7 +167,7 @@ struct RpcModule : RTLIL::Module { std::string parameter_info; for (auto ¶m : parameters) { - log("Parameter %s = %s\n", param.first.c_str(), log_signal(RTLIL::SigSpec(param.second))); + log("Parameter %s = %s\n", param.first, log_signal(RTLIL::SigSpec(param.second))); parameter_info += stringf("%s=%s", param.first, log_signal(RTLIL::SigSpec(param.second))); } @@ -180,7 +180,7 @@ struct RpcModule : RTLIL::Module { derived_name = "$paramod" + stripped_name + parameter_info; if (design->has(derived_name)) { - log("Found cached RTLIL representation for module `%s'.\n", derived_name.c_str()); + log("Found cached RTLIL representation for module `%s'.\n", derived_name); } else { std::string command, input; std::tie(command, input) = server->derive_module(stripped_name.substr(1), parameters); @@ -437,7 +437,7 @@ struct RpcFrontend : public Pass { command_path_len_w = SearchPathW(/*lpPath=*/NULL, /*lpFileName=*/command_w.c_str(), /*lpExtension=*/L".exe", /*nBufferLength=*/0, /*lpBuffer=*/NULL, /*lpFilePart=*/NULL); if (command_path_len_w == 0) { - log_error("SearchPathW failed: %s\n", get_last_error_str().c_str()); + log_error("SearchPathW failed: %s\n", get_last_error_str()); goto cleanup_exec; } command_path_w.resize(command_path_len_w - 1); @@ -448,19 +448,19 @@ struct RpcFrontend : public Pass { pipe_attr.bInheritHandle = TRUE; pipe_attr.lpSecurityDescriptor = NULL; if (!CreatePipe(&send_r, &send_w, &pipe_attr, /*nSize=*/0)) { - log_error("CreatePipe failed: %s\n", get_last_error_str().c_str()); + log_error("CreatePipe failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!SetHandleInformation(send_w, HANDLE_FLAG_INHERIT, 0)) { - log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str()); + log_error("SetHandleInformation failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!CreatePipe(&recv_r, &recv_w, &pipe_attr, /*nSize=*/0)) { - log_error("CreatePipe failed: %s\n", get_last_error_str().c_str()); + log_error("CreatePipe failed: %s\n", get_last_error_str()); goto cleanup_exec; } if (!SetHandleInformation(recv_r, HANDLE_FLAG_INHERIT, 0)) { - log_error("SetHandleInformation failed: %s\n", get_last_error_str().c_str()); + log_error("SetHandleInformation failed: %s\n", get_last_error_str()); goto cleanup_exec; } @@ -470,7 +470,7 @@ struct RpcFrontend : public Pass { startup_info.hStdError = GetStdHandle(STD_ERROR_HANDLE); startup_info.dwFlags |= STARTF_USESTDHANDLES; if (!CreateProcessW(/*lpApplicationName=*/command_path_w.c_str(), /*lpCommandLine=*/&command_line_w[0], /*lpProcessAttributes=*/NULL, /*lpThreadAttributes=*/NULL, /*bInheritHandles=*/TRUE, /*dwCreationFlags=*/0, /*lpEnvironment=*/NULL, /*lpCurrentDirectory=*/NULL, &startup_info, &proc_info)) { - log_error("CreateProcessW failed: %s\n", get_last_error_str().c_str()); + log_error("CreateProcessW failed: %s\n", get_last_error_str()); goto cleanup_exec; } CloseHandle(proc_info.hProcess); @@ -550,7 +550,7 @@ cleanup_exec: h = CreateFileW(path_w.c_str(), GENERIC_READ|GENERIC_WRITE, /*dwShareMode=*/0, /*lpSecurityAttributes=*/NULL, /*dwCreationDisposition=*/OPEN_EXISTING, /*dwFlagsAndAttributes=*/0, /*hTemplateFile=*/NULL); if (h == INVALID_HANDLE_VALUE) { - log_error("CreateFileW failed: %s\n", get_last_error_str().c_str()); + log_error("CreateFileW failed: %s\n", get_last_error_str()); goto cleanup_path; } @@ -586,7 +586,7 @@ cleanup_path: log_cmd_error("Failed to connect to RPC frontend.\n"); for (auto &module_name : server->get_module_names()) { - log("Linking module `%s'.\n", module_name.c_str()); + log("Linking module `%s'.\n", module_name); RpcModule *module = new RpcModule; module->name = "$abstract\\" + module_name; module->server = server; diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 2c1910d13..e8d6ac9c9 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -90,7 +90,7 @@ struct RTLILFrontend : public Frontend { } extra_args(f, filename, args, argidx); - log("Input filename: %s\n", filename.c_str()); + log("Input filename: %s\n", filename); RTLIL_FRONTEND::lexin = f; RTLIL_FRONTEND::current_design = design; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d4bedf44f..9e3436c14 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -143,7 +143,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); else - log("%s%s\n", message_prefix.c_str(), message.c_str()); + log("%s%s\n", message_prefix, message); } if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR)) verific_error_msg = message; @@ -250,7 +250,7 @@ static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ) { if (val.size()==3 && val[0]=='\'' && val.back()=='\'') return RTLIL::Const::from_string(val.substr(1,val.size()-2)); - log_error("Error parsing VHDL %s.\n", typ.c_str()); + log_error("Error parsing VHDL %s.\n", typ); } static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ) @@ -261,7 +261,7 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string c.flags |= RTLIL::CONST_FLAG_SIGNED; return c; } - log_error("Error parsing VHDL %s.\n", typ.c_str()); + log_error("Error parsing VHDL %s.\n", typ); } static const RTLIL::Const extract_vhdl_integer(std::string &val) @@ -2655,7 +2655,7 @@ struct VerificExtNets cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner(); } - log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str()); + log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A), get_full_netlist_name(B)); } void run(Netlist *nl) @@ -2679,17 +2679,17 @@ struct VerificExtNets continue; if (verific_verbose) - log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name()); + log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl), inst->Name(), port->Name()); Netlist *ext_nl = net->Owner(); if (verific_verbose) - log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str()); + log(" external net owner: %s\n", get_full_netlist_name(ext_nl)); Netlist *ca_nl = find_common_ancestor(nl, ext_nl); if (verific_verbose) - log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str()); + log(" common ancestor: %s\n", get_full_netlist_name(ca_nl)); Net *ca_net = route_up(net, !port->IsOutput(), ca_nl); Net *new_net = ca_net; @@ -3038,7 +3038,7 @@ std::string verific_import(Design *design, const std::mapChangePortBusStructures(1 /* hierarchical */); @@ -3060,7 +3060,7 @@ std::string verific_import(Design *design, const std::map 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r')) break; @@ -4232,7 +4232,7 @@ struct VerificPass : public Pass { } lines.sort(); for (auto &line : lines) - log("verific -cfg %s\n", line.c_str()); + log("verific -cfg %s\n", line); goto check_error; } @@ -4291,7 +4291,7 @@ struct VerificPass : public Pass { } if (!verific_error_msg.empty()) - log_error("%s\n", verific_error_msg.c_str()); + log_error("%s\n", verific_error_msg); } #else /* YOSYS_ENABLE_VERIFIC */ diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 8b98997f6..cc5f07004 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1024,7 +1024,7 @@ struct VerificSvaImporter [[noreturn]] void parser_error(std::string errmsg) { if (!importer->mode_keep) - log_error("%s", errmsg.c_str()); + log_error("%s", errmsg); log_warning("%s", errmsg.c_str()); throw ParserErrorException(); } diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 7d011b68e..8674758ab 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -242,7 +242,7 @@ struct arg_map_t void add_arg(const std::string &name, const char *default_value) { if (find(name)) { - log_error("Duplicate macro arguments with name `%s'.\n", name.c_str()); + log_error("Duplicate macro arguments with name `%s'.\n", name); } name_to_pos[name] = args.size(); @@ -789,14 +789,14 @@ frontend_verilog_preproc(std::istream &f, else if (ifdef_pass_level > 0) ifdef_pass_level--; else - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); continue; } if (tok == "`else") { if (ifdef_fail_level == 0) { if (ifdef_pass_level == 0) - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); ifdef_pass_level--; ifdef_fail_level = 1; ifdef_already_satisfied = true; @@ -813,7 +813,7 @@ frontend_verilog_preproc(std::istream &f, std::string name = next_token(true); if (ifdef_fail_level == 0) { if (ifdef_pass_level == 0) - log_error("Found %s outside of macro conditional branch!\n", tok.c_str()); + log_error("Found %s outside of macro conditional branch!\n", tok); ifdef_pass_level--; ifdef_fail_level = 1; ifdef_already_satisfied = true; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 4b4f7ad8d..589b80f8d 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -497,7 +497,7 @@ struct VerilogFrontend : public Frontend { if (!flag_nopp) { code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode); if (flag_ppdump) - log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); + log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc); parse_state.lexin = new std::istringstream(code_after_preproc); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb61e05df..d61fa7830 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -3261,7 +3261,7 @@ basic_expr: ConstParser p{@4}; auto val = p.const2ast(*$4, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); if (val == nullptr) - log_error("Value conversion failed: `%s'\n", $4->c_str()); + log_error("Value conversion failed: `%s'\n", *$4); $$ = std::make_unique(@$, AST_TO_BITS, std::move($2), std::move(val)); } | hierarchical_id integral_number { @@ -3274,7 +3274,7 @@ basic_expr: auto val = p.const2ast(*$2, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); SET_AST_NODE_LOC(val.get(), @2, @2); if (val == nullptr) - log_error("Value conversion failed: `%s'\n", $2->c_str()); + log_error("Value conversion failed: `%s'\n", *$2); $$ = std::make_unique(@$, AST_TO_BITS, std::move(bits), std::move(val)); } | integral_number { @@ -3282,7 +3282,7 @@ basic_expr: $$ = p.const2ast(*$1, extra->case_type_stack.size() == 0 ? 0 : extra->case_type_stack.back(), !mode->lib); SET_AST_NODE_LOC($$.get(), @1, @1); if ($$ == nullptr) - log_error("Value conversion failed: `%s'\n", $1->c_str()); + log_error("Value conversion failed: `%s'\n", *$1); } | TOK_REALVAL { $$ = std::make_unique(@$, AST_REALVALUE); diff --git a/kernel/driver.cc b/kernel/driver.cc index 76c11853e..bbe4e46f3 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -585,7 +585,7 @@ int main(int argc, char **argv) FILE *scriptfp = fopen(scriptfile.c_str(), "r"); if (scriptfp == nullptr) { - log_error("Failed to open file '%s' for reading.\n", scriptfile.c_str()); + log_error("Failed to open file '%s' for reading.\n", scriptfile); } if (PyRun_SimpleFile(scriptfp, scriptfile.c_str()) != 0) { log_flush(); @@ -664,7 +664,7 @@ int main(int argc, char **argv) log("Warnings: %d experimental features used (not excluded with -x).\n", GetSize(log_experimentals)); #ifdef _WIN32 - log("End of script. Logfile hash: %s\n", hash.c_str()); + log("End of script. Logfile hash: %s\n", hash); #else std::string meminfo; std::string stats_divider = ", "; @@ -690,7 +690,7 @@ int main(int argc, char **argv) meminfo = stringf(", MEM: %.2f MB peak", ru_buffer.ru_maxrss / (1024.0 * 1024.0)); #endif - log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash.c_str(), + log("End of script. Logfile hash: %s%sCPU: user %.2fs system %.2fs%s\n", hash, stats_divider.c_str(), ru_buffer.ru_utime.tv_sec + 1e-6 * ru_buffer.ru_utime.tv_usec, ru_buffer.ru_stime.tv_sec + 1e-6 * ru_buffer.ru_stime.tv_usec, meminfo.c_str()); #endif @@ -768,9 +768,9 @@ int main(int argc, char **argv) f = fopen(filename.c_str(), "a+"); if (f == NULL) - log_error("Can't create coverage file `%s'.\n", filename.c_str()); + log_error("Can't create coverage file `%s'.\n", filename); - log("\n", filename.c_str()); + log("\n", filename); for (auto &it : get_coverage_data()) fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 35e7a2865..cc558d418 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -35,7 +35,7 @@ FstData::FstData(std::string filename) : ctx(nullptr) filename_trim.erase(filename_trim.size()-4); tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir(), filename_trim); std::string cmd = stringf("vcd2fst %s %s", filename, tmp_file); - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); filename = tmp_file; @@ -44,7 +44,7 @@ FstData::FstData(std::string filename) : ctx(nullptr) const std::vector g_units = { "s", "ms", "us", "ns", "ps", "fs", "as", "zs" }; ctx = (fstReaderContext *)fstReaderOpen(filename.c_str()); if (!ctx) - log_error("Error opening '%s' as FST file\n", filename.c_str()); + log_error("Error opening '%s' as FST file\n", filename); int scale = (int)fstReaderGetTimescale(ctx); timescale = pow(10.0, scale); timescale_str = ""; diff --git a/kernel/functional.cc b/kernel/functional.cc index 211527926..de8e7e8fc 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -395,7 +395,7 @@ public: Node y = neg_if(y_flipped, sign(b)); return factory.extend(y, y_width, true); } else - log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str()); + log_error("unhandled cell in CellSimplifier %s\n", cellType); } else { if(cellType.in(ID($mod), ID($modfloor))) return factory.extend(factory.unsigned_mod(a, b), y_width, false); @@ -458,9 +458,9 @@ public: return factory.value(state); } } else if(cellType == ID($check)) { - log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName.c_str()); + log_error("The design contains a $check cell `%s'. This is not supported by the functional backend. Call `chformal -lower' to avoid this error.\n", cellName); } else { - log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str()); + log_error("`%s' cells are not supported by the functional backend\n", cellType); } } }; @@ -744,7 +744,7 @@ void IR::topological_sort() { log_warning("Combinational loop:\n"); for (int *i = begin; i != end; ++i) { Node node(_graph[*i]); - log("- %s = %s\n", RTLIL::unescape_id(node.name()).c_str(), node.to_string().c_str()); + log("- %s = %s\n", RTLIL::unescape_id(node.name()), node.to_string()); } log("\n"); scc = true; @@ -836,7 +836,7 @@ void Writer::print_impl(const char *fmt, vector> &fns) else p = pe; if(index >= fns.size()) - log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt).c_str()); + log_error("invalid format string: index %zu out of bounds (%zu): \"%s\"\n", index, fns.size(), quote_fmt(fmt)); fns[index](); next_index = index + 1; } @@ -844,7 +844,7 @@ void Writer::print_impl(const char *fmt, vector> &fns) case '}': p++; if(*p != '}') - log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt).c_str()); + log_error("invalid format string: unescaped }: \"%s\"\n", quote_fmt(fmt)); *os << '}'; break; default: diff --git a/kernel/functional.h b/kernel/functional.h index 7e5becef4..073adf40a 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -552,17 +552,17 @@ namespace Functional { } IRInput &add_input(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._inputs.emplace({name, kind}, IRInput(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("input `%s` was re-defined", name.c_str()); + if (!inserted) log_error("input `%s` was re-defined", name); return it->second; } IROutput &add_output(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._outputs.emplace({name, kind}, IROutput(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("output `%s` was re-defined", name.c_str()); + if (!inserted) log_error("output `%s` was re-defined", name); return it->second; } IRState &add_state(IdString name, IdString kind, Sort sort) { auto [it, inserted] = _ir._states.emplace({name, kind}, IRState(_ir, name, kind, std::move(sort))); - if (!inserted) log_error("state `%s` was re-defined", name.c_str()); + if (!inserted) log_error("state `%s` was re-defined", name); return it->second; } Node value(IRInput const& input) { diff --git a/kernel/gzip.cc b/kernel/gzip.cc index 24907d8cf..d19c06579 100644 --- a/kernel/gzip.cc +++ b/kernel/gzip.cc @@ -121,7 +121,7 @@ std::istream* uncompressed(const std::string filename, std::ios_base::openmode m } if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) { #ifdef YOSYS_ENABLE_ZLIB - log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str()); + log("Found gzip magic in file `%s', decompressing using zlib.\n", filename); if (magic[2] != 8) log_cmd_error("gzip file `%s' uses unsupported compression type %02x\n", filename.c_str(), unsigned(magic[2])); diff --git a/kernel/log.cc b/kernel/log.cc index 0dd56a04f..494047cde 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -228,7 +228,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s for (int c : header_count) header_id += stringf("%s%d", header_id.empty() ? "" : ".", c); - log("%s. ", header_id.c_str()); + log("%s. ", header_id); log_formatted_string(format, std::move(str)); log_flush(); @@ -237,7 +237,7 @@ void log_formatted_header(RTLIL::Design *design, std::string_view format, std::s if (log_hdump.count(header_id) && design != nullptr) for (auto &filename : log_hdump.at(header_id)) { - log("Dumping current design to '%s'.\n", filename.c_str()); + log("Dumping current design to '%s'.\n", filename); if (yosys_xtrace) IdString::xtrace_db_dump(); Pass::call(design, {"dump", "-o", filename}); @@ -635,21 +635,21 @@ void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_cell(buf, indent, cell); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_wire(RTLIL::Wire *wire, std::string indent) { std::stringstream buf; RTLIL_BACKEND::dump_wire(buf, indent, wire); - log("%s", buf.str().c_str()); + log("%s", buf.str()); } void log_check_expected() @@ -668,7 +668,7 @@ void log_check_expected() auto check = [&](const std::string kind, std::string pattern, LogExpectedItem item) { if (item.current_count == 0) { log_warn_regexes.clear(); - log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str()); + log_error("Expected %s pattern '%s' not found !\n", kind, pattern); } if (item.current_count != item.expected_count) { log_warn_regexes.clear(); @@ -689,7 +689,7 @@ void log_check_expected() auto check_err = [&](const std::string kind, std::string pattern, LogExpectedItem item) { if (item.current_count == item.expected_count) { log_warn_regexes.clear(); - log("Expected %s pattern '%s' found !!!\n", kind.c_str(), pattern.c_str()); + log("Expected %s pattern '%s' found !!!\n", kind, pattern); yosys_shutdown(); #ifdef EMSCRIPTEN throw 0; @@ -700,7 +700,7 @@ void log_check_expected() #endif } else { log_warn_regexes.clear(); - log_error("Expected %s pattern '%s' not found !\n", kind.c_str(), pattern.c_str()); + log_error("Expected %s pattern '%s' not found !\n", kind, pattern); } }; for (auto &[pattern, item] : expect_error) diff --git a/kernel/log.h b/kernel/log.h index 5143524bf..2a33953ff 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -424,7 +424,7 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false") static inline void log_dump_val_worker(double v) { log("%f", v); } static inline void log_dump_val_worker(char *v) { log("%s", v); } static inline void log_dump_val_worker(const char *v) { log("%s", v); } -static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); } +static inline void log_dump_val_worker(std::string v) { log("%s", v); } static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); } static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); } void log_dump_val_worker(RTLIL::IdString v); diff --git a/kernel/log_help.cc b/kernel/log_help.cc index 30c06a7c3..93b91b08b 100644 --- a/kernel/log_help.cc +++ b/kernel/log_help.cc @@ -85,7 +85,7 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead if (leading_newline) log("\n"); for (std::string line; std::getline(iss, line);) { - log("%s", indent_str.c_str()); + log("%s", indent_str); auto curr_len = indent_str.length(); std::istringstream lss(line); for (std::string word; std::getline(lss, word, ' ');) { @@ -93,10 +93,10 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead word = word.substr(1, word.length()-2); if (curr_len + word.length() >= MAX_LINE_LEN-1) { curr_len = 0; - log("\n%s", indent_str.c_str()); + log("\n%s", indent_str); } if (word.length()) { - log("%s ", word.c_str()); + log("%s ", word); curr_len += word.length() + 1; } } diff --git a/kernel/register.cc b/kernel/register.cc index c82620f40..4afd7ada3 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -54,7 +54,7 @@ Pass::Pass(std::string name, std::string short_help, source_location location) : void Pass::run_register() { if (pass_register.count(pass_name) && !replace_existing_pass()) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; } @@ -123,7 +123,7 @@ void Pass::help() prettyHelp.log_help(); } else { log("\n"); - log("No help message for command `%s'.\n", pass_name.c_str()); + log("No help message for command `%s'.\n", pass_name); log("\n"); } } @@ -143,7 +143,7 @@ void Pass::cmd_log_args(const std::vector &args) return; log("Full command line:"); for (size_t i = 0; i < args.size(); i++) - log(" %s", args[i].c_str()); + log(" %s", args[i]); log("\n"); } @@ -158,7 +158,7 @@ void Pass::cmd_error(const std::vector &args, size_t argidx, std::s command_text = command_text + (command_text.empty() ? "" : " ") + args[i]; } - log("\nSyntax error in command `%s':\n", command_text.c_str()); + log("\nSyntax error in command `%s':\n", command_text); help(); log_cmd_error("Command syntax error: %s\n> %s\n> %*s^\n", @@ -257,7 +257,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) if (echo_mode) { log("%s", create_prompt(design, 0)); for (size_t i = 0; i < args.size(); i++) - log("%s%s", i ? " " : "", args[i].c_str()); + log("%s%s", i ? " " : "", args[i]); log("\n"); } @@ -330,9 +330,9 @@ bool ScriptPass::check_label(std::string label, std::string info) if (active_design == nullptr) { log("\n"); if (info.empty()) - log(" %s:\n", label.c_str()); + log(" %s:\n", label); else - log(" %s: %s\n", label.c_str(), info.c_str()); + log(" %s: %s\n", label, info); return true; } else { if (!active_run_from.empty() && active_run_from == active_run_to) { @@ -351,9 +351,9 @@ void ScriptPass::run(std::string command, std::string info) { if (active_design == nullptr) { if (info.empty()) - log(" %s\n", command.c_str()); + log(" %s\n", command); else - log(" %s %s\n", command.c_str(), info.c_str()); + log(" %s %s\n", command, info); } else { Pass::call(active_design, command); active_design->check(); @@ -364,9 +364,9 @@ void ScriptPass::run_nocheck(std::string command, std::string info) { if (active_design == nullptr) { if (info.empty()) - log(" %s\n", command.c_str()); + log(" %s\n", command); else - log(" %s %s\n", command.c_str(), info.c_str()); + log(" %s %s\n", command, info); } else { Pass::call(active_design, command); } @@ -402,11 +402,11 @@ Frontend::Frontend(std::string name, std::string short_help, source_location loc void Frontend::run_register() { if (pass_register.count(pass_name) && !replace_existing_pass()) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; if (frontend_register.count(frontend_name) && !replace_existing_pass()) - log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name.c_str()); + log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name); frontend_register[frontend_name] = this; } @@ -462,7 +462,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector 0 && (buffer[buffer.size() - 1] == '\n' || buffer[buffer.size() - 1] == '\r')) break; @@ -548,11 +548,11 @@ Backend::Backend(std::string name, std::string short_help, source_location locat void Backend::run_register() { if (pass_register.count(pass_name)) - log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); + log_error("Unable to register pass '%s', pass already exists!\n", pass_name); pass_register[pass_name] = this; if (backend_register.count(backend_name)) - log_error("Unable to register backend '%s', backend already exists!\n", backend_name.c_str()); + log_error("Unable to register backend '%s', backend already exists!\n", backend_name); backend_register[backend_name] = this; } @@ -699,12 +699,12 @@ static void log_warning_flags(Pass *pass) { if (pass->experimental_flag) { if (!has_warnings) log("\n"); has_warnings = true; - log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name.c_str()); + log("WARNING: THE '%s' COMMAND IS EXPERIMENTAL.\n", name); } if (pass->internal_flag) { if (!has_warnings) log("\n"); has_warnings = true; - log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name.c_str()); + log("WARNING: THE '%s' COMMAND IS INTENDED FOR INTERNAL DEVELOPER USE ONLY.\n", name); } if (has_warnings) log("\n"); @@ -966,7 +966,7 @@ struct HelpPass : public Pass { auto cell_pair = pair(cell_help, it.second); cells.emplace(name, cell_pair); } else { - log("ERROR: Missing cell help for cell '%s'.\n", name.c_str()); + log("ERROR: Missing cell help for cell '%s'.\n", name); raise_error |= true; } } @@ -1028,7 +1028,7 @@ struct HelpPass : public Pass { if (args.size() == 1) { log("\n"); for (auto &it : pass_register) - log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str()); + log(" %-20s %s\n", it.first, it.second->short_help); log("\n"); log("Type 'help ' for more information on a command.\n"); log("Type 'help -cells' for a list of all cell types.\n"); @@ -1040,7 +1040,7 @@ struct HelpPass : public Pass { if (args[1] == "-all") { for (auto &it : pass_register) { log("\n\n"); - log("%s -- %s\n", it.first.c_str(), it.second->short_help.c_str()); + log("%s -- %s\n", it.first, it.second->short_help); for (size_t i = 0; i < it.first.size() + it.second->short_help.size() + 6; i++) log("="); log("\n"); @@ -1052,7 +1052,7 @@ struct HelpPass : public Pass { log("\n"); for (auto &it : cell_help_messages.cell_help) { SimHelper help_cell = it.second; - log(" %-15s %s\n", help_cell.name.c_str(), help_cell.ports.c_str()); + log(" %-15s %s\n", help_cell.name, help_cell.ports); } log("\n"); log("Type 'help ' for more information on a cell type.\n"); @@ -1067,34 +1067,34 @@ struct HelpPass : public Pass { auto help_cell = cell_help_messages.get(args[1]); if (is_code_getter(args[1])) { log("\n"); - log("%s\n", help_cell.code.c_str()); + log("%s\n", help_cell.code); } else { - log("\n %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str()); + log("\n %s %s\n\n", help_cell.name, help_cell.ports); if (help_cell.ver == "2" || help_cell.ver == "2a") { - if (help_cell.title != "") log("%s:\n", help_cell.title.c_str()); + if (help_cell.title != "") log("%s:\n", help_cell.title); std::stringstream ss; ss << help_cell.desc; for (std::string line; std::getline(ss, line, '\n');) { - if (line != "::") log("%s\n", line.c_str()); + if (line != "::") log("%s\n", line); } } else if (help_cell.desc.length()) { - log("%s\n", help_cell.desc.c_str()); + log("%s\n", help_cell.desc); } else { log("No help message for this cell type found.\n"); } - log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str()); + log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1]); log("\n"); } } else - log("No such command or cell type: %s\n", args[1].c_str()); + log("No such command or cell type: %s\n", args[1]); return; } else if (args.size() == 3) { // this option is undocumented as it is for internal use only if (args[1] == "-dump-cmds-json") { PrettyJson json; if (!json.write_to_file(args[2])) - log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno)); if (dump_cmds_json(json)) { log_abort(); } @@ -1103,13 +1103,13 @@ struct HelpPass : public Pass { else if (args[1] == "-dump-cells-json") { PrettyJson json; if (!json.write_to_file(args[2])) - log_error("Can't open file `%s' for writing: %s\n", args[2].c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", args[2], strerror(errno)); if (dump_cells_json(json)) { log_error("One or more cells defined in celltypes.h are missing help documentation.\n"); } } else - log("Unknown help command: `%s %s'\n", args[1].c_str(), args[2].c_str()); + log("Unknown help command: `%s %s'\n", args[1], args[2]); return; } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 352fbb84e..3a8b25d1d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1056,7 +1056,7 @@ void RTLIL::Design::add(RTLIL::Binding *binding) RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name) { if (modules_.count(name) != 0) - log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str()); + log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name); log_assert(refcount_modules_ == 0); RTLIL::Module *module = new RTLIL::Module; diff --git a/kernel/sexpr.cc b/kernel/sexpr.cc index 0b977d2a8..bea3376a0 100644 --- a/kernel/sexpr.cc +++ b/kernel/sexpr.cc @@ -119,7 +119,7 @@ void SExprWriter::print(SExpr const &sexpr, bool close, bool indent_rest) { _pending_nl = true; } }else - log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string().c_str()); + log_error("shouldn't happen: SExpr '%s' is neither an atom nor a list", sexpr.to_string()); } void SExprWriter::close(size_t n) { diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 31d008404..4bdb680ac 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -87,7 +87,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a tcl_command_name = "renames"; Tcl_CmdInfo info; if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { - log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); + log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first); } else { std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name, it.first); Tcl_Eval(interp, tcl_script.c_str()); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 46dc6a76f..dc640fae9 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -710,7 +710,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } else if (filename == "-") { command = "script"; } else { - log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename.c_str()); + log_error("Can't guess frontend for input file `%s' (missing -f option)!\n", filename); } } @@ -731,7 +731,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi from_to_active = run_from.empty(); } - log("\n-- Executing script file `%s' --\n", filename.c_str()); + log("\n-- Executing script file `%s' --\n", filename); FILE *f = stdin; @@ -741,7 +741,7 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } if (f == NULL) - log_error("Can't open script file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + log_error("Can't open script file `%s' for reading: %s\n", filename, strerror(errno)); FILE *backup_script_file = Frontend::current_script_file; Frontend::current_script_file = f; @@ -790,9 +790,9 @@ bool run_frontend(std::string filename, std::string command, RTLIL::Design *desi } if (filename == "-") { - log("\n-- Parsing stdin using frontend `%s' --\n", command.c_str()); + log("\n-- Parsing stdin using frontend `%s' --\n", command); } else { - log("\n-- Parsing `%s' using frontend `%s' --\n", filename.c_str(), command.c_str()); + log("\n-- Parsing `%s' using frontend `%s' --\n", filename, command); } if (command[0] == ' ') { @@ -811,7 +811,7 @@ void run_pass(std::string command, RTLIL::Design *design) if (design == nullptr) design = yosys_design; - log("\n-- Running command `%s' --\n", command.c_str()); + log("\n-- Running command `%s' --\n", command); Pass::call(design, command); } @@ -843,16 +843,16 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig else if (filename.empty()) return; else - log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename.c_str()); + log_error("Can't guess backend for output file `%s' (missing -b option)!\n", filename); } if (filename.empty()) filename = "-"; if (filename == "-") { - log("\n-- Writing to stdout using backend `%s' --\n", command.c_str()); + log("\n-- Writing to stdout using backend `%s' --\n", command); } else { - log("\n-- Writing to `%s' using backend `%s' --\n", filename.c_str(), command.c_str()); + log("\n-- Writing to `%s' using backend `%s' --\n", filename, command); } Backend::backend_call(design, NULL, filename, command); diff --git a/kernel/yw.cc b/kernel/yw.cc index f36212c7f..daad53380 100644 --- a/kernel/yw.cc +++ b/kernel/yw.cc @@ -108,38 +108,38 @@ ReadWitness::ReadWitness(const std::string &filename) : { std::ifstream f(filename.c_str()); if (f.fail() || GetSize(filename) == 0) - log_error("Cannot open file `%s`\n", filename.c_str()); + log_error("Cannot open file `%s`\n", filename); std::stringstream buf; buf << f.rdbuf(); std::string err; json11::Json json = json11::Json::parse(buf.str(), err); if (!err.empty()) - log_error("Failed to parse `%s`: %s\n", filename.c_str(), err.c_str()); + log_error("Failed to parse `%s`: %s\n", filename, err); std::string format = json["format"].string_value(); if (format.empty()) - log_error("Failed to parse `%s`: Unknown format\n", filename.c_str()); + log_error("Failed to parse `%s`: Unknown format\n", filename); if (format != "Yosys Witness Trace") - log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename.c_str(), format.c_str()); + log_error("Failed to parse `%s`: Unsupported format `%s`\n", filename, format); for (auto &clock_json : json["clocks"].array_items()) { Clock clock; clock.path = get_path(clock_json["path"]); if (clock.path.empty()) - log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Missing path for clock `%s`\n", filename, clock_json.dump()); auto edge_str = clock_json["edge"]; if (edge_str.string_value() == "posedge") clock.is_posedge = true; else if (edge_str.string_value() == "negedge") clock.is_negedge = true; else - log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown edge type for clock `%s`\n", filename, clock_json.dump()); if (!clock_json["offset"].is_number()) - log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown offset for clock `%s`\n", filename, clock_json.dump()); clock.offset = clock_json["offset"].int_value(); if (clock.offset < 0) - log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename.c_str(), clock_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid offset for clock `%s`\n", filename, clock_json.dump()); clocks.push_back(clock); } @@ -149,18 +149,18 @@ ReadWitness::ReadWitness(const std::string &filename) : signal.bits_offset = bits_offset; signal.path = get_path(signal_json["path"]); if (signal.path.empty()) - log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Missing path for signal `%s`\n", filename, signal_json.dump()); if (!signal_json["width"].is_number()) - log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown width for signal `%s`\n", filename, signal_json.dump()); signal.width = signal_json["width"].int_value(); if (signal.width < 0) - log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid width for signal `%s`\n", filename, signal_json.dump()); bits_offset += signal.width; if (!signal_json["offset"].is_number()) - log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Unknown offset for signal `%s`\n", filename, signal_json.dump()); signal.offset = signal_json["offset"].int_value(); if (signal.offset < 0) - log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename.c_str(), signal_json.dump().c_str()); + log_error("Failed to parse `%s`: Invalid offset for signal `%s`\n", filename, signal_json.dump()); signal.init_only = signal_json["init_only"].bool_value(); signals.push_back(signal); } @@ -168,11 +168,11 @@ ReadWitness::ReadWitness(const std::string &filename) : for (auto &step_json : json["steps"].array_items()) { Step step; if (!step_json["bits"].is_string()) - log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename.c_str(), GetSize(steps)); + log_error("Failed to parse `%s`: Expected string as bits value for step %d\n", filename, GetSize(steps)); step.bits = step_json["bits"].string_value(); for (char c : step.bits) { if (c != '0' && c != '1' && c != 'x' && c != '?') - log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename.c_str(), c, GetSize(steps)); + log_error("Failed to parse `%s`: Invalid bit '%c' value for step %d\n", filename, c, GetSize(steps)); } steps.push_back(step); } diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index 907a16fe0..e475ba71c 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -67,7 +67,7 @@ struct Slice { int wire_offset(RTLIL::Wire *wire, int index) const { int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index); if (rtl_offset < 0 || rtl_offset >= wire->width) { - log_error("Slice %s is out of bounds for wire %s in module %s", to_string().c_str(), log_id(wire), log_id(wire->module)); + log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module)); } return rtl_offset; } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 833d6006d..0d395f043 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -38,22 +38,22 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const log_assert(is_formal_celltype(celltype)); if (wire == nullptr) { - log_error("Could not find wire with name \"%s\".\n", name.c_str()); + log_error("Could not find wire with name \"%s\".\n", name); } else { RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); formal_cell->setPort(ID::A, wire); if(enable_name == "") { formal_cell->setPort(ID::EN, State::S1); - log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str()); + log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name); } else { RTLIL::Wire *enable_wire = module->wire(escaped_enable_name); if(enable_wire == nullptr) - log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str()); + log_error("Could not find enable wire with name \"%s\".\n", enable_name); formal_cell->setPort(ID::EN, enable_wire); - log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str()); + log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name); } } } @@ -79,7 +79,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (wire == nullptr) log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); - log("Module %s already has such an object.\n", module->name.c_str()); + log("Module %s already has such an object.\n", module->name); } else { @@ -91,7 +91,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n module->fixup_ports(); } - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + log("Added wire %s to module %s.\n", name, module->name); } if (!flag_global) @@ -110,7 +110,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; cell->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str()); + log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type); } } diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 47354f1d5..bab00c287 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -146,7 +146,7 @@ struct CoverPass : public Pass { for (auto f : out_files) fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); if (do_log) - log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str()); + log("%-60s %10d %s\n", it.second.first, it.second.second, it.first); } #else for (auto f : out_files) diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 933bd457f..9324cf630 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -105,7 +105,7 @@ struct EdgetypePass : public Pass { edge_cache.sort(); for (auto &str : edge_cache) - log("%s\n", str.c_str()); + log("%s\n", str); } } EdgetypePass; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index 486fa1c2b..b346fc95d 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -172,7 +172,7 @@ struct ExecPass : public Pass { std::string line = linebuf.substr(0, pos); linebuf.erase(0, pos + 1); if (!flag_quiet) - log("%s\n", line.c_str()); + log("%s\n", line); if (flag_expect_stdout) for(auto &x : expect_stdout) diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 60324702c..d7264d392 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -343,7 +343,7 @@ private: //with taint signals and connect the new ports to the corresponding taint signals. RTLIL::Module *cell_module_def = module->design->module(cell->type); dict orig_ports = cell->connections(); - log("Adding cell %s\n", cell_module_def->name.c_str()); + log("Adding cell %s\n", cell_module_def->name); for (auto &it : orig_ports) { RTLIL::SigSpec port = it.second; RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port); diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc index 00456b8f9..65e74cc04 100644 --- a/passes/cmds/internal_stats.cc +++ b/passes/cmds/internal_stats.cc @@ -100,15 +100,15 @@ struct InternalStatsPass : public Pass { if (json_mode) { log("{\n"); - log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str()); + log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump()); std::stringstream invocation; std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " ")); - log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str()); + log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump()); if (auto mem = current_mem_bytes()) { - log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str()); + log(" \"memory_now\": %s,\n", std::to_string(*mem)); } auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode); - log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str()); + log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes)); } // stats go here diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 9a88dec7f..6898f33f5 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -85,7 +85,7 @@ struct CoveragePass : public Pass { if (!ofile.empty()) { fout.open(ofile, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", ofile.c_str()); + log_error("Could not open file \"%s\" with write access.\n", ofile); } std::map> uncovered_lines; @@ -128,7 +128,7 @@ struct CoveragePass : public Pass { for (const auto& file_entry : all_lines) { int lines_found = file_entry.second.size(); int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0); - log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found); + log("File %s: %d/%d lines covered\n", file_entry.first, lines_hit, lines_found); if(!ofile.empty()) { fout << "SF:" << file_entry.first << "\n"; diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 391eaea2e..57759fc90 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -106,7 +106,7 @@ struct LogPass : public Pass { if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end); if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end); if (to_log) { - if (!header) log("%s%s", text.c_str(), line_end); + if (!header) log("%s%s", text, line_end); else log_header(design, "%s%s", text.c_str(), line_end); } } diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index a9762f630..37240bb7e 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -108,7 +108,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to warn list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to warn list.\n", pattern); log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -120,7 +120,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to nowarn list.\n", pattern); log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -132,7 +132,7 @@ struct LoggerPass : public Pass { std::string pattern = args[++argidx]; if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { - log("Added regex '%s' for warnings to werror list.\n", pattern.c_str()); + log("Added regex '%s' for warnings to werror list.\n", pattern); log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { @@ -152,7 +152,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-experimental" && argidx+1 < args.size()) { std::string value = args[++argidx]; - log("Added '%s' experimental ignore list.\n", value.c_str()); + log("Added '%s' experimental ignore list.\n", value); log_experimentals_ignored.insert(value); continue; } diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index a653844b7..6c7921d53 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -187,11 +187,11 @@ struct PluginPass : public Pass { log("Loaded plugins:\n"); for (auto &it : loaded_plugins) - log(" %s\n", it.first.c_str()); + log(" %s\n", it.first); #ifdef WITH_PYTHON for (auto &it : loaded_python_plugins) - log(" %s\n", it.first.c_str()); + log(" %s\n", it.first); #endif if (!loaded_plugin_aliases.empty()) { @@ -200,7 +200,7 @@ struct PluginPass : public Pass { for (auto &it : loaded_plugin_aliases) max_alias_len = max(max_alias_len, GetSize(it.first)); for (auto &it : loaded_plugin_aliases) - log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str()); + log("Alias: %-*s %s\n", max_alias_len, it.first, it.second); } } } diff --git a/passes/cmds/portarcs.cc b/passes/cmds/portarcs.cc index 73ca98d88..36870489a 100644 --- a/passes/cmds/portarcs.cc +++ b/passes/cmds/portarcs.cc @@ -278,7 +278,7 @@ struct PortarcsPass : Pass { log("\n"); for (auto bit : outputs) { - log(" %10s ", bit_str(bit).c_str()); + log(" %10s ", bit_str(bit)); int *p = annotations.at(canonical_bit(bit)); for (auto i = 0; i < inputs.size(); i++) log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay); diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index f78d9d3b6..b109ce22a 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -75,7 +75,7 @@ struct PortlistPass : public Pass { } log("module %s%s\n", log_id(module), m_mode ? " (" : ""); for (int i = 0; i < GetSize(ports); i++) - log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : ""); + log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : ""); if (m_mode) log(");\nendmodule\n"); }; diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index c8b0a1d1f..e4e78b0ea 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass { static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) { if (x.flags & RTLIL::CONST_FLAG_STRING) - log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str()); + log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string()); else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED) - log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str()); + log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string()); else log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail } @@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass { for (auto mod : design->selected_modules()) { if (design->selected_whole_module(mod)) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name)); + log("%s%s\n", get_indent_str(indent), log_id(mod->name)); indent += 2; for (auto &it : mod->attributes) log_const(it.first, it.second, indent); } for (auto cell : mod->selected_cells()) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name)); + log("%s%s\n", get_indent_str(indent), log_id(cell->name)); indent += 2; for (auto &it : cell->attributes) log_const(it.first, it.second, indent); @@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass { } for (auto wire : mod->selected_wires()) { - log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name)); + log("%s%s\n", get_indent_str(indent), log_id(wire->name)); indent += 2; for (auto &it : wire->attributes) log_const(it.first, it.second, indent); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 1f3d0992e..c4bb7135e 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -577,7 +577,7 @@ struct RenamePass : public Pass { new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name)); auto new_name = new_wire_names[wire].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) - log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str()); + log_error("Failed to rename wire %s -> %s\n", name, new_name); } for (auto cell : module->selected_cells()) { @@ -590,7 +590,7 @@ struct RenamePass : public Pass { new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name)); auto new_name = new_cell_names[cell].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) - log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str()); + log_error("Failed to rename cell %s -> %s\n", name, new_name); } for (auto &it : new_wire_names) @@ -629,7 +629,7 @@ struct RenamePass : public Pass { if (module_to_rename != nullptr) { to_name = RTLIL::escape_id(to_name); - log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str()); + log("Renaming module %s to %s.\n", module_to_rename->name, to_name); design->rename(module_to_rename, to_name); } else log_cmd_error("Object `%s' not found!\n", from_name.c_str()); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index e55e63828..680531f25 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -101,7 +101,7 @@ struct SccWorker design(design), module(module), sigmap(module) { if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); return; } diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 4a63f2f60..f64ce943c 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -76,18 +76,18 @@ struct ScratchpadPass : public Pass { if (args[argidx] == "-get" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier)) { - log("%s\n", design->scratchpad_get_string(identifier).c_str()); + log("%s\n", design->scratchpad_get_string(identifier)); } else if (RTLIL::constpad.count(identifier)) { - log("%s\n", RTLIL::constpad.at(identifier).c_str()); + log("%s\n", RTLIL::constpad.at(identifier)); } else { - log("\"%s\" not set\n", identifier.c_str()); + log("\"%s\" not set\n", identifier); } continue; } if (args[argidx] == "-set" && argidx+2 < args.size()) { string identifier = args[++argidx]; if (RTLIL::constpad.count(identifier)) - log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str()); + log_error("scratchpad entry \"%s\" is a global constant\n", identifier); string value = args[++argidx]; if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2); design->scratchpad_set_string(identifier, value); @@ -107,9 +107,9 @@ struct ScratchpadPass : public Pass { else if (RTLIL::constpad.count(identifier_from)) value = RTLIL::constpad.at(identifier_from); else - log_error("\"%s\" not set\n", identifier_from.c_str()); + log_error("\"%s\" not set\n", identifier_from); if (RTLIL::constpad.count(identifier_to)) - log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str()); + log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to); design->scratchpad_set_string(identifier_to, value); continue; } @@ -118,7 +118,7 @@ struct ScratchpadPass : public Pass { string expected = args[++argidx]; if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2); if (design->scratchpad.count(identifier) == 0) - log_error("scratchpad entry '%s' is not defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is not defined\n", identifier); string value = design->scratchpad_get_string(identifier); if (value != expected) { log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n", @@ -129,13 +129,13 @@ struct ScratchpadPass : public Pass { if (args[argidx] == "-assert-set" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier) == 0) - log_error("scratchpad entry '%s' is not defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is not defined\n", identifier); continue; } if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) { string identifier = args[++argidx]; if (design->scratchpad.count(identifier) > 0) - log_error("scratchpad entry '%s' is defined\n", identifier.c_str()); + log_error("scratchpad entry '%s' is defined\n", identifier); continue; } break; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 901f923f8..7fcf5cfcd 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -632,20 +632,20 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char if (rule.cell_types.size() > 0) { log(" cell types:"); for (auto &it : rule.cell_types) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } if (rule.port_names.size() > 0) { log(" port names:"); for (auto &it : rule.port_names) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } } if (limits.size() > 0) { log(" limits:"); for (auto &it : limits) - log(" %s", it.c_str()); + log(" %s", it); log("\n"); } #endif @@ -1443,7 +1443,7 @@ struct SelectPass : public Pass { std::ifstream f(read_file); yosys_input_files.insert(read_file); if (f.fail()) - log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno)); + log_error("Can't open '%s' for reading: %s\n", read_file, strerror(errno)); auto sel = RTLIL::Selection::EmptySelection(design); string line; @@ -1518,7 +1518,7 @@ struct SelectPass : public Pass { f = fopen(write_file.c_str(), "w"); yosys_output_files.insert(write_file); if (f == nullptr) - log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno)); + log_error("Can't open '%s' for writing: %s\n", write_file, strerror(errno)); } if (work_stack.size() > 0) design->push_selection(work_stack.back()); @@ -1573,7 +1573,7 @@ struct SelectPass : public Pass { RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); std::string desc = describe_selection_for_assert(design, sel, true); - log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str()); + log_error("Assertion failed: selection is not empty:%s\n%s", sel_str, desc); } return; } @@ -1588,7 +1588,7 @@ struct SelectPass : public Pass { RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); std::string desc = describe_selection_for_assert(design, sel, true); - log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str()); + log_error("Assertion failed: selection is empty:%s\n%s", sel_str, desc); } return; } @@ -1645,7 +1645,7 @@ struct SelectPass : public Pass { if (!unset_name.empty()) { if (!design->selection_vars.erase(unset_name)) - log_error("Selection '%s' does not exist!\n", unset_name.c_str()); + log_error("Selection '%s' does not exist!\n", unset_name); return; } diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index dce33c05b..c4a555e6a 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -41,7 +41,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width if (module->count_id(name) != 0) { - log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + log("Module %s already has such an object %s.\n", module->name, name); name += "$"; return add_wire(module, name, width, flag_input, flag_output); } @@ -56,7 +56,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width module->fixup_ports(); } - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + log("Added wire %s to module %s.\n", name, module->name); } return wire; @@ -319,7 +319,7 @@ struct SetundefPass : public Pass { wire = add_wire(module, name, c.width, true, false); module->connect(RTLIL::SigSig(c, wire)); } - log("Exposing undriven wire %s as input.\n", wire->name.c_str()); + log("Exposing undriven wire %s as input.\n", wire->name); } module->fixup_ports(); } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 9ea29bc4e..49032a0e0 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -188,7 +188,7 @@ struct ShowWorker if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; - log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str()); + log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id); } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { @@ -895,7 +895,7 @@ struct ShowPass : public Pass { f.open(filename.c_str()); yosys_input_files.insert(filename); if (f.fail()) - log_error("Can't open lib file `%s'.\n", filename.c_str()); + log_error("Can't open lib file `%s'.\n", filename); RTLIL::Design *lib = new RTLIL::Design; Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); libs.push_back(lib); @@ -907,7 +907,7 @@ struct ShowPass : public Pass { std::string dot_file = stringf("%s.dot", prefix); std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format); - log("Writing dot description to `%s'.\n", dot_file.c_str()); + log("Writing dot description to `%s'.\n", dot_file); FILE *f = fopen(dot_file.c_str(), "w"); if (custom_prefix) yosys_output_files.insert(dot_file); @@ -934,7 +934,7 @@ struct ShowPass : public Pass { #endif std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); #if !defined(YOSYS_DISABLE_SPAWN) if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); @@ -954,7 +954,7 @@ struct ShowPass : public Pass { #else std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } else @@ -964,7 +964,7 @@ struct ShowPass : public Pass { #else std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 4ad0d2b25..2993c3d3a 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -345,7 +345,7 @@ struct SplicePass : public Pass { for (auto module : design->selected_modules()) { if (module->processes.size()) { - log("Skipping module %s as it contains processes.\n", module->name.c_str()); + log("Skipping module %s as it contains processes.\n", module->name); continue; } diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 9281f3327..1b9e6106c 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -285,7 +285,7 @@ struct statdata_t { cell_area.at(cell_type).is_sequential = cell_data.is_sequential; } } else { - log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type.c_str(), + log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type, (int)cell_data.double_parameter_area.size()); } } @@ -452,22 +452,22 @@ struct statdata_t { if (print_area) { if (print_hierarchical) { - log(" %s %s %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), count_local_str.c_str(), + log(" %s %s %s %s %s%s\n", count_global_str, area_global_str, count_local_str, area_local_str.c_str(), indent.c_str(), name.c_str()); } else if (print_global_only) { - log(" %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_global_str, area_global_str, indent, name); } else { if (count_local > 0) - log(" %s %s %s%s\n", count_local_str.c_str(), area_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_local_str, area_local_str, indent, name); } } else { if (print_hierarchical) { - log(" %s %s %s%s\n", count_global_str.c_str(), count_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s %s%s\n", count_global_str, count_local_str, indent, name); } else if (print_global_only) { - log(" %s %s%s\n", count_global_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s%s\n", count_global_str, indent, name); } else { if (count_local > 0) - log(" %s %s%s\n", count_local_str.c_str(), indent.c_str(), name.c_str()); + log(" %s %s%s\n", count_local_str, indent, name); } } } @@ -540,13 +540,13 @@ struct statdata_t { if (!unknown_cell_area.empty()) { log("\n"); for (auto cell_type : unknown_cell_area) - log(" Area for cell type %s is unknown!\n", cell_type.c_str()); + log(" Area for cell type %s is unknown!\n", cell_type); } if (area != 0) { log("\n"); if (print_hierarchical || print_global_only) { - log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area); log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area); } else { double local_area = 0; @@ -555,7 +555,7 @@ struct statdata_t { double local_sequential_area = 0; for (auto &it : local_seq_area_cells_by_type) local_sequential_area += it.second; - log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area); log(" of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area, 100.0 * local_sequential_area / local_area); } @@ -587,19 +587,19 @@ struct statdata_t { if (!first_module) log(",\n"); if (hierarchical) { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); - log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0).c_str()); - log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0).c_str()); - log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0).c_str()); - log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0).c_str()); - log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0).c_str()); - log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0).c_str()); - log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0).c_str()); - log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0).c_str()); - log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0).c_str()); - log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area).c_str()); - log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area).c_str()); - log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area).c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); + log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0)); + log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0)); + log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0)); + log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0)); + log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0)); + log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0)); + log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0)); + log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0)); + log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0)); + log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area)); + log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area)); + log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area)); log(" \"num_cells_by_type\": {\n"); bool first_line = true; @@ -607,7 +607,7 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(), + log(" %s: %s", json11::Json(log_id(it.first)).dump(), json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0, local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second, area_cells_by_type.at(it.first)) @@ -621,7 +621,7 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(), + log(" %s: %s", json11::Json(log_id(it.first)).dump(), json_line(0, 0, it.second, submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0) .c_str()); @@ -640,7 +640,7 @@ struct statdata_t { } else { if (global_only) { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); log(" \"num_wires\": %u,\n", num_wires); log(" \"num_wire_bits\": %u,\n", num_wire_bits); log(" \"num_pub_wires\": %u,\n", num_pub_wires); @@ -662,20 +662,20 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } for (auto &it : num_submodules_by_type) if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } log("\n"); log(" }"); } else { - log(" %s: {\n", json11::Json(mod_name).dump().c_str()); + log(" %s: {\n", json11::Json(mod_name).dump()); log(" \"num_wires\": %u,\n", local_num_wires); log(" \"num_wire_bits\": %u,\n", local_num_wire_bits); log(" \"num_pub_wires\": %u,\n", local_num_pub_wires); @@ -697,14 +697,14 @@ struct statdata_t { if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } for (auto &it : num_submodules_by_type) if (it.second) { if (!first_line) log(",\n"); - log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second); + log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second); first_line = false; } log("\n"); @@ -824,11 +824,11 @@ void read_liberty_cellarea(dict &cell_area, string libert double value = std::stod(s); single_parameter_area.push_back(value); } catch (const std::exception &e) { - log_error("Failed to parse single parameter area value '%s': %s\n", s.c_str(), e.what()); + log_error("Failed to parse single parameter area value '%s': %s\n", s, e.what()); } } if (single_parameter_area.size() == 0) - log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1].c_str()); + log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1]); // check if it is a double parameterised area } const LibertyAst *dar = cell->find("double_area_parameterised"); @@ -857,12 +857,12 @@ void read_liberty_cellarea(dict &cell_area, string libert value = std::stod(s); cast_sub_array.push_back(value); } catch (const std::exception &e) { - log_error("Failed to parse double parameter area value for '%s': %s\n", s.c_str(), e.what()); + log_error("Failed to parse double parameter area value for '%s': %s\n", s, e.what()); } } double_parameter_area.push_back(cast_sub_array); if (cast_sub_array.size() == 0) - log_error("double paramter array has size 0: %s\n", s.c_str()); + log_error("double paramter array has size 0: %s\n", s); } } const LibertyAst *par = cell->find("port_names"); @@ -973,10 +973,10 @@ struct StatPass : public Pass { if (json_mode) { log("{\n"); - log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str()); + log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump()); std::stringstream invocation; std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " ")); - log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str()); + log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump()); log(" \"modules\": {\n"); } diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index f0e4943de..86a529520 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -322,7 +322,7 @@ struct EstimateSta { std::string src_attr = cell->get_src_attribute(); cell_src = stringf(" source: %s", src_attr); } - log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str()); + log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src); printed.insert(cell); } } else { @@ -333,7 +333,7 @@ struct EstimateSta { std::string src_attr = bit.wire->get_src_attribute(); wire_src = stringf(" source: %s", src_attr); } - log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]); + log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src, levels[node]); } } diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 323b9cb34..fd45d6ba0 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -988,7 +988,7 @@ struct VizPass : public Pass { if (custom_prefix) yosys_output_files.insert(dot_file); - log("Writing dot description to `%s'.\n", dot_file.c_str()); + log("Writing dot description to `%s'.\n", dot_file); FILE *f = nullptr; auto open_dot_file = [&]() { if (f != nullptr) return; @@ -1028,7 +1028,7 @@ struct VizPass : public Pass { #endif std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file); #undef DOT_CMD - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); #if !defined(YOSYS_DISABLE_SPAWN) if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); @@ -1047,7 +1047,7 @@ struct VizPass : public Pass { #else std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } else @@ -1057,7 +1057,7 @@ struct VizPass : public Pass { #else std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background); #endif - log("Exec: %s\n", cmd.c_str()); + log("Exec: %s\n", cmd); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } diff --git a/passes/cmds/wrapcell.cc b/passes/cmds/wrapcell.cc index f7d9fbeed..4c6f44ed7 100644 --- a/passes/cmds/wrapcell.cc +++ b/passes/cmds/wrapcell.cc @@ -59,7 +59,7 @@ std::optional format_with_params(std::string fmt, const dict format_with_params(std::string fmt, const dicttype.c_str(), cell->name.c_str()); + log(" merging %s cell %s.\n", cell->type, cell->name); merged_set.insert(cell); already_optimized = false; @@ -243,7 +243,7 @@ struct FsmExpand void execute() { log("\n"); - log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str()); + log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name); already_optimized = false; limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int(); diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 65dda1267..7c79a53cc 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -76,7 +76,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st kiss_file.open(kiss_name, std::ios::out | std::ios::trunc); if (!kiss_file.is_open()) { - log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str()); + log_error("Could not open file \"%s\" with write access.\n", kiss_name); } fsm_data.copy_from_cell(cell); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index a0fd50097..d83cff5cdc 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -71,7 +71,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL { RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) { - log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); + log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name); return false; } @@ -255,7 +255,7 @@ undef_bit_in_next_state: static void extract_fsm(RTLIL::Wire *wire) { - log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str()); + log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name); // get input and output signals for state ff @@ -274,7 +274,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q) continue; - log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); + log(" found %s cell for state register: %s\n", cell->type, cell->name); RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q)); RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D)); clk = cell->getPort(ID::CLK); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 711a81db2..8a18d259a 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapname.c_str(), module->name.c_str()); + log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name, module->name); FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 2db011cd0..99771f90a 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -293,7 +293,7 @@ struct FsmOpt FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module) { - log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str()); + log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name); fsm_data.copy_from_cell(cell); this->cell = cell; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index bcdea9d87..8ee03329f 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -56,15 +56,15 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs { std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto"; - log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str()); + log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding); if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { - log(" unknown encoding `%s': using auto instead.\n", encoding.c_str()); + log(" unknown encoding `%s': using auto instead.\n", encoding); encoding = "auto"; } if (encoding == "none" || encoding == "user") { - log(" nothing to do for encoding `%s'.\n", encoding.c_str()); + log(" nothing to do for encoding `%s'.\n", encoding); return; } @@ -79,7 +79,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs encoding = default_encoding; else encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary"; - log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str()); + log(" mapping auto encoding to `%s` for this FSM.\n", encoding); } if (encoding == "one-hot") { @@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs } fsm_data.state_bits = new_num_state_bits; } else - log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); + log_error("FSM encoding `%s' is not supported!\n", encoding); if (encfile) fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str()); @@ -113,7 +113,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs } else log_abort(); - log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str()); + log(" %s -> %s\n", fsm_data.state_table[i].as_string(), new_code.as_string()); if (encfile) fprintf(encfile, ".map %s %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str()); fsm_data.state_table[i] = new_code; @@ -165,13 +165,13 @@ struct FsmRecodePass : public Pass { if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) { fm_set_fsm_file = fopen(args[++argidx].c_str(), "w"); if (fm_set_fsm_file == NULL) - log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno)); + log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx], strerror(errno)); continue; } if (arg == "-encfile" && argidx+1 < args.size() && encfile == NULL) { encfile = fopen(args[++argidx].c_str(), "w"); if (encfile == NULL) - log_error("Can't open encfile `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno)); + log_error("Can't open encfile `%s' for writing: %s\n", args[argidx], strerror(errno)); continue; } if (arg == "-encoding" && argidx+1 < args.size() && default_encoding.empty()) { diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 1c6aaf65f..9aa12241e 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -134,7 +134,7 @@ struct FsmData { log("-------------------------------------\n"); log("\n"); - log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str()); + log(" Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string()); log("\n"); log(" Number of input signals: %3d\n", num_inputs); log(" Number of output signals: %3d\n", num_outputs); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 69ef744ca..6fec628c2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -59,7 +59,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, std::set portnames; std::set parameters; std::map portwidths; - log("Generate module for cell type %s:\n", celltype.c_str()); + log("Generate module for cell type %s:\n", celltype); for (auto mod : design->modules()) for (auto cell : mod->cells()) @@ -605,9 +605,9 @@ void hierarchy_worker(RTLIL::Design *design, std::setname.c_str()); + log("Top module: %s\n", mod->name); else if (!mod->get_blackbox_attribute()) - log("Used module: %*s%s\n", indent, "", mod->name.c_str()); + log("Used module: %*s%s\n", indent, "", mod->name); used.insert(mod); for (auto cell : mod->cells()) { @@ -647,7 +647,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) for (auto mod : del_modules) { if (!purge_lib && mod->get_blackbox_attribute()) continue; - log("Removing unused module `%s'.\n", mod->name.c_str()); + log("Removing unused module `%s'.\n", mod->name); design->remove(mod); del_counter++; } @@ -873,11 +873,11 @@ struct HierarchyPass : public Pass { log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output"); if (decl.index >= 1) log(" [at position %d]", decl.index); - log(" %s\n", decl.portname.c_str()); + log(" %s\n", decl.portname); generate_ports.push_back(decl); continue; is_celltype: - log("Celltype: %s\n", args[argidx].c_str()); + log("Celltype: %s\n", args[argidx]); generate_cells.push_back(RTLIL::unescape_id(args[argidx])); } continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 8d88a8919..d77d65359 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker void handle_submodule(SubModule &submod) { - log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str()); + log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name); wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { @@ -192,13 +192,13 @@ struct SubmodWorker } if (new_wire->port_input && new_wire->port_output) - log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: inout %s\n", wire->name, new_wire->name); else if (new_wire->port_input) - log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: input %s\n", wire->name, new_wire->name); else if (new_wire->port_output) - log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str()); + log(" signal %s: output %s\n", wire->name, new_wire->name); else - log(" signal %s: internal\n", wire->name.c_str()); + log(" signal %s: internal\n", wire->name); flags.new_wire = new_wire; } @@ -214,7 +214,7 @@ struct SubmodWorker log_assert(wire_flags.count(bit.wire) > 0); bit.wire = wire_flags.at(bit.wire).new_wire; } - log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str()); + log(" cell %s (%s)\n", new_cell->name, new_cell->type); if (!copy_mode) module->remove(cell); } @@ -250,12 +250,12 @@ struct SubmodWorker return; if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); return; } if (module->memories.size() > 0) { - log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str()); + log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name); return; } diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index fb256e41c..61589cab0 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -134,7 +134,7 @@ struct Parser { rewrite_filename(filename); infile.open(filename); if (infile.fail()) { - log_error("failed to open %s\n", filename.c_str()); + log_error("failed to open %s\n", filename); } parse(); infile.close(); @@ -181,14 +181,14 @@ struct Parser { void eat_token(std::string expected) { std::string token = get_token(); if (token != expected) { - log_error("%s:%d: expected `%s`, got `%s`.\n", filename.c_str(), line_number, expected.c_str(), token.c_str()); + log_error("%s:%d: expected `%s`, got `%s`.\n", filename, line_number, expected, token); } } IdString get_id() { std::string token = get_token(); if (token.empty() || (token[0] != '$' && token[0] != '\\')) { - log_error("%s:%d: expected id string, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected id string, got `%s`.\n", filename, line_number, token); } return IdString(token); } @@ -203,14 +203,14 @@ struct Parser { if (!isalnum(c) && c != '_') valid = false; if (!valid) - log_error("%s:%d: expected name, got `%s`.\n", filename.c_str(), line_number, res.c_str()); + log_error("%s:%d: expected name, got `%s`.\n", filename, line_number, res); return res; } std::string get_string() { std::string token = get_token(); if (token.size() < 2 || token[0] != '"' || token[token.size()-1] != '"') { - log_error("%s:%d: expected string, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected string, got `%s`.\n", filename, line_number, token); } return token.substr(1, token.size()-2); } @@ -225,7 +225,7 @@ struct Parser { char *endptr; long res = strtol(token.c_str(), &endptr, 0); if (token.empty() || *endptr || res > INT_MAX) { - log_error("%s:%d: expected int, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected int, got `%s`.\n", filename, line_number, token); } return res; } @@ -235,7 +235,7 @@ struct Parser { char *endptr; double res = strtod(token.c_str(), &endptr); if (token.empty() || *endptr) { - log_error("%s:%d: expected float, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected float, got `%s`.\n", filename, line_number, token); } return res; } @@ -248,7 +248,7 @@ struct Parser { void get_semi() { std::string token = get_token(); if (token != ";") { - log_error("%s:%d: expected `;`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `;`, got `%s`.\n", filename, line_number, token); } } @@ -387,7 +387,7 @@ struct Parser { exit_portoption(); } else if (token == "clock") { if (port.kind == PortKind::Ar) { - log_error("%s:%d: `clock` not allowed in async read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `clock` not allowed in async read port.\n", filename, line_number); } ClockDef def; token = get_token(); @@ -398,7 +398,7 @@ struct Parser { } else if (token == "negedge") { def.kind = ClkPolKind::Negedge; } else { - log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `posedge`, `negedge`, or `anyedge`, got `%s`.\n", filename, line_number, token); } if (peek_string()) { def.name = get_string(); @@ -407,13 +407,13 @@ struct Parser { add_cap(port.clock, def); } else if (token == "clken") { if (port.kind == PortKind::Ar) { - log_error("%s:%d: `clken` not allowed in async read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `clken` not allowed in async read port.\n", filename, line_number); } get_semi(); add_cap(port.clken, {}); } else if (token == "wrbe_separate") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) { - log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrbe_separate` not allowed in read port.\n", filename, line_number); } get_semi(); add_cap(port.wrbe_separate, {}); @@ -424,14 +424,14 @@ struct Parser { if (token == "tied") { get_token(); if (!is_rw) - log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `tied` only makes sense for read+write ports.\n", filename, line_number); while (peek_int()) def.wr_widths.push_back(get_int()); def.tied = true; } else if (token == "mix") { get_token(); if (!is_rw) - log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `mix` only makes sense for read+write ports.\n", filename, line_number); while (peek_int()) def.wr_widths.push_back(get_int()); def.rd_widths = def.wr_widths; @@ -439,7 +439,7 @@ struct Parser { } else if (token == "rd") { get_token(); if (!is_rw) - log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rd` only makes sense for read+write ports.\n", filename, line_number); do { def.rd_widths.push_back(get_int()); } while (peek_int()); @@ -451,7 +451,7 @@ struct Parser { } else if (token == "wr") { get_token(); if (!is_rw) - log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wr` only makes sense for read+write ports.\n", filename, line_number); do { def.wr_widths.push_back(get_int()); } while (peek_int()); @@ -470,12 +470,12 @@ struct Parser { add_cap(port.width, def); } else if (token == "rden") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rden` only allowed on sync read ports.\n", filename, line_number); get_semi(); add_cap(port.rden, {}); } else if (token == "rdwr") { if (port.kind != PortKind::Srsw) - log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `rdwr` only allowed on sync read+write ports.\n", filename, line_number); RdWrKind kind; token = get_token(); if (token == "undefined") { @@ -489,13 +489,13 @@ struct Parser { } else if (token == "new_only") { kind = RdWrKind::NewOnly; } else { - log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `undefined`, `new`, `old`, `new_only`, or `no_change`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdwr, kind); } else if (token == "rdinit") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); ResetValKind kind; token = get_token(); if (token == "none") { @@ -507,13 +507,13 @@ struct Parser { } else if (token == "no_undef") { kind = ResetValKind::NoUndef; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, or `no_undef`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdinit, kind); } else if (token == "rdarst") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); ResetValKind kind; token = get_token(); if (token == "none") { @@ -527,13 +527,13 @@ struct Parser { } else if (token == "init") { kind = ResetValKind::Init; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.rdarst, kind); } else if (token == "rdsrst") { if (port.kind != PortKind::Sr && port.kind != PortKind::Srsw) - log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: `%s` only allowed on sync read ports.\n", filename, line_number, token); SrstDef def; token = get_token(); if (token == "none") { @@ -547,7 +547,7 @@ struct Parser { } else if (token == "init") { def.val = ResetValKind::Init; } else { - log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `none`, `zero`, `any`, `no_undef`, or `init`, got `%s`.\n", filename, line_number, token); } if (def.val == ResetValKind::None) { def.kind = SrstKind::None; @@ -560,7 +560,7 @@ struct Parser { } else if (token == "gated_rden") { def.kind = SrstKind::GatedRdEn; } else { - log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `ungated`, `gated_clken` or `gated_rden`, got `%s`.\n", filename, line_number, token); } } def.block_wr = false; @@ -572,14 +572,14 @@ struct Parser { add_cap(port.rdsrst, def); } else if (token == "wrprio") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) - log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrprio` only allowed on write ports.\n", filename, line_number); do { add_cap(port.wrprio, get_string()); } while (peek_string()); get_semi(); } else if (token == "wrtrans") { if (port.kind == PortKind::Ar || port.kind == PortKind::Sr) - log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename.c_str(), line_number); + log_error("%s:%d: `wrtrans` only allowed on write ports.\n", filename, line_number); token = peek_token(); RawWrTransDef def; if (token == "all") { @@ -595,7 +595,7 @@ struct Parser { } else if (token == "old") { def.kind = WrTransKind::Old; } else { - log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `new` or `old`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(port.wrtrans, def); @@ -609,9 +609,9 @@ struct Parser { get_semi(); add_cap(port.optional_rw, {}); } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing port item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing port item.\n", filename, line_number); } else { - log_error("%s:%d: unknown port-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown port-level item `%s`.\n", filename, line_number, token); } } @@ -646,14 +646,14 @@ struct Parser { } else if (token == "abits") { int val = get_int(); if (val < 0) - log_error("%s:%d: abits %d nagative.\n", filename.c_str(), line_number, val); + log_error("%s:%d: abits %d nagative.\n", filename, line_number, val); get_semi(); add_cap(ram.abits, val); } else if (token == "width") { WidthsDef def; int w = get_int(); if (w <= 0) - log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w); + log_error("%s:%d: width %d not positive.\n", filename, line_number, w); def.widths.push_back(w); def.mode = WidthMode::Single; get_semi(); @@ -664,9 +664,9 @@ struct Parser { do { int w = get_int(); if (w <= 0) - log_error("%s:%d: width %d not positive.\n", filename.c_str(), line_number, w); + log_error("%s:%d: width %d not positive.\n", filename, line_number, w); if (w < last * 2) - log_error("%s:%d: width %d smaller than %d required for progression.\n", filename.c_str(), line_number, w, last * 2); + log_error("%s:%d: width %d smaller than %d required for progression.\n", filename, line_number, w, last * 2); last = w; def.widths.push_back(w); } while(peek_int()); @@ -676,7 +676,7 @@ struct Parser { } else if (token == "per_port") { def.mode = WidthMode::PerPort; } else { - log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `global`, or `per_port`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(ram.widths, def); @@ -702,7 +702,7 @@ struct Parser { } else if (token == "byte") { int val = get_int(); if (val <= 0) - log_error("%s:%d: byte width %d not positive.\n", filename.c_str(), line_number, val); + log_error("%s:%d: byte width %d not positive.\n", filename, line_number, val); add_cap(ram.byte, val); get_semi(); } else if (token == "init") { @@ -717,7 +717,7 @@ struct Parser { } else if (token == "none") { kind = MemoryInitKind::None; } else { - log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `zero`, `any`, `none`, or `no_undef`, got `%s`.\n", filename, line_number, token); } get_semi(); add_cap(ram.init, kind); @@ -743,7 +743,7 @@ struct Parser { } else if (token == "srsw") { port.kind = PortKind::Srsw; } else { - log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `ar`, `sr`, `sw`, `arsw`, or `srsw`, got `%s`.\n", filename, line_number, token); } do { port.names.push_back(get_string()); @@ -752,9 +752,9 @@ struct Parser { if (active) add_cap(ram.ports, port); } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing ram item.\n", filename, line_number); } else { - log_error("%s:%d: unknown ram-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown ram-level item `%s`.\n", filename, line_number, token); } } @@ -787,7 +787,7 @@ struct Parser { } else if (token == "huge") { ram.kind = RamKind::Huge; } else { - log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: expected `distributed`, `block`, or `huge`, got `%s`.\n", filename, line_number, token); } ram.id = get_id(); parse_ram_block(); @@ -795,9 +795,9 @@ struct Parser { compile_ram(orig_line); } } else if (token == "") { - log_error("%s:%d: unexpected EOF while parsing top item.\n", filename.c_str(), line_number); + log_error("%s:%d: unexpected EOF while parsing top item.\n", filename, line_number); } else { - log_error("%s:%d: unknown top-level item `%s`.\n", filename.c_str(), line_number, token.c_str()); + log_error("%s:%d: unknown top-level item `%s`.\n", filename, line_number, token); } } @@ -816,7 +816,7 @@ struct Parser { if (!opts_ok(cap.portopts, portopts)) continue; if (res) - log_error("%s:%d: duplicate %s cap.\n", filename.c_str(), line_number, name); + log_error("%s:%d: duplicate %s cap.\n", filename, line_number, name); res = &cap.val; } return res; @@ -860,7 +860,7 @@ struct Parser { } else { const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock"); if (!cdef) - log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line); + log_error("%s:%d: missing clock capability.\n", filename, orig_line); var.clk_pol = cdef->kind; if (cdef->name.empty()) { var.clk_shared = -1; @@ -876,7 +876,7 @@ struct Parser { } else { var.clk_shared = it->second; if (cram.shared_clocks[var.clk_shared].anyedge != anyedge) { - log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename.c_str(), orig_line, cdef->name.c_str()); + log_error("%s:%d: named clock \"%s\" used with both posedge/negedge and anyedge clocks.\n", filename, orig_line, cdef->name); } } } @@ -885,7 +885,7 @@ struct Parser { const PortWidthDef *wdef = find_single_cap(pdef.width, cram.options, portopts, "width"); if (wdef) { if (cram.width_mode != WidthMode::PerPort) - log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename.c_str(), orig_line); + log_error("%s:%d: per-port width doesn't make sense for tied dbits.\n", filename, orig_line); compile_widths(var, cram.dbits, *wdef); } else { var.width_tied = true; @@ -908,9 +908,9 @@ struct Parser { var.rdsrstmode = srv->kind; var.rdsrst_block_wr = srv->block_wr; if (srv->kind == SrstKind::GatedClkEn && !var.clk_en) - log_error("%s:%d: `gated_clken` used without `clken`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `gated_clken` used without `clken`.\n", filename, orig_line); if (srv->kind == SrstKind::GatedRdEn && !var.rd_en) - log_error("%s:%d: `gated_rden` used without `rden`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `gated_rden` used without `rden`.\n", filename, orig_line); } else { var.rdsrstval = ResetValKind::None; var.rdsrstmode = SrstKind::None; @@ -918,13 +918,13 @@ struct Parser { } if (var.rdarstval == ResetValKind::Init || var.rdsrstval == ResetValKind::Init) { if (var.rdinitval != ResetValKind::Any && var.rdinitval != ResetValKind::NoUndef) { - log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename.c_str(), orig_line); + log_error("%s:%d: reset value `init` has to be paired with `any` or `no_undef` initial value.\n", filename, orig_line); } } } var.wrbe_separate = find_single_cap(pdef.wrbe_separate, cram.options, portopts, "wrbe_separate"); if (var.wrbe_separate && cram.byte == 0) { - log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename.c_str(), orig_line); + log_error("%s:%d: `wrbe_separate` used without `byte`.\n", filename, orig_line); } for (auto &def: pdef.wrprio) { if (!opts_ok(def.opts, cram.options)) @@ -948,18 +948,18 @@ struct Parser { grp.variants.push_back(var); } if (grp.variants.empty()) { - log_error("%s:%d: all port option combinations are forbidden.\n", filename.c_str(), orig_line); + log_error("%s:%d: all port option combinations are forbidden.\n", filename, orig_line); } cram.port_groups.push_back(grp); } void compile_ram(int orig_line) { if (ram.abits.empty()) - log_error("%s:%d: `dims` capability should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: `dims` capability should be specified.\n", filename, orig_line); if (ram.widths.empty()) - log_error("%s:%d: `widths` capability should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: `widths` capability should be specified.\n", filename, orig_line); if (ram.ports.empty()) - log_error("%s:%d: at least one port group should be specified.\n", filename.c_str(), orig_line); + log_error("%s:%d: at least one port group should be specified.\n", filename, orig_line); for (auto opts: make_opt_combinations(ram.opts)) { bool forbidden = false; for (auto &fdef: ram.forbid) { @@ -1003,7 +1003,7 @@ struct Parser { const int *byte = find_single_cap(ram.byte, opts, Options(), "byte"); cram.byte = byte ? *byte : 0; if (GetSize(cram.dbits) - 1 > cram.abits) - log_error("%s:%d: abits %d too small for dbits progression.\n", filename.c_str(), line_number, cram.abits); + log_error("%s:%d: abits %d too small for dbits progression.\n", filename, line_number, cram.abits); validate_byte(widths->widths, cram.byte); const MemoryInitKind *ik = find_single_cap(ram.init, opts, Options(), "init"); cram.init = ik ? *ik : MemoryInitKind::None; @@ -1037,18 +1037,18 @@ struct Parser { if (widths[0] % byte == 0) { for (int j = 1; j < GetSize(widths); j++) if (widths[j] % byte != 0) - log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte); return; } for (int i = 0; i < GetSize(widths); i++) { if (widths[i] == byte) { for (int j = i + 1; j < GetSize(widths); j++) if (widths[j] % byte != 0) - log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: width progression past byte width %d is not divisible.\n", filename, line_number, byte); return; } } - log_error("%s:%d: byte width %d invalid for dbits.\n", filename.c_str(), line_number, byte); + log_error("%s:%d: byte width %d invalid for dbits.\n", filename, line_number, byte); } void compile_widths(PortVariant &var, const std::vector &widths, const PortWidthDef &width) { @@ -1073,13 +1073,13 @@ struct Parser { if (dbits[i] == widths[0]) { for (int j = 0; j < GetSize(widths); j++) { if (i+j >= GetSize(dbits) || dbits[i+j] != widths[j]) { - log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename.c_str(), line_number, widths[j]); + log_error("%s:%d: port width %d doesn't match dbits progression.\n", filename, line_number, widths[j]); } } return {i, i + GetSize(widths) - 1}; } } - log_error("%s:%d: port width %d invalid for dbits.\n", filename.c_str(), line_number, widths[0]); + log_error("%s:%d: port width %d invalid for dbits.\n", filename, line_number, widths[0]); } void parse() { diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 9bc8ad9b0..8ef2c4271 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -369,7 +369,7 @@ struct rules_t attr_icase = false; if (infile.fail()) - log_error("Can't open rules file `%s'.\n", filename.c_str()); + log_error("Can't open rules file `%s'.\n", filename); while (next_line()) { @@ -1020,7 +1020,7 @@ void handle_memory(Mem &mem, const rules_t &rules, FfInitVals *initvals) log(" Properties:"); for (auto &it : match_properties) - log(" %s=%d", it.first.c_str(), it.second); + log(" %s=%d", it.first, it.second); log("\n"); pool> failed_brams; diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 75c6e6a3a..916b21233 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -334,7 +334,7 @@ struct MemoryDffWorker void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str()); + log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, module->name); std::vector muxdata; SigSpec data = walk_muxes(port.data, muxdata); @@ -554,7 +554,7 @@ struct MemoryDffWorker void handle_rd_port_addr(Mem &mem, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port address `%s'[%d] in module `%s': ", mem.memid.c_str(), idx, module->name.c_str()); + log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, module->name); FfData ff; pool> bits; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 4c7d9636d..0fb4608b1 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -548,20 +548,20 @@ void MemMapping::determine_style() { // Nothing. } else if (val_s == "logic" || val_s == "registers") { kind = RamKind::Logic; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "distributed") { kind = RamKind::Distributed; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") { kind = RamKind::Block; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "huge" || val_s == "ultra") { kind = RamKind::Huge; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid)); } else { kind = RamKind::NotLogic; style = val_s; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid), val_s.c_str()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s, log_id(mem.module->name), log_id(mem.memid), val_s); } return; } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 126ec65b5..cc8dce13e 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -192,7 +192,7 @@ struct MemoryMapWorker } } - log("Mapping memory %s in module %s:\n", mem.memid.c_str(), module->name.c_str()); + log("Mapping memory %s in module %s:\n", mem.memid, module->name); int abits = ceil_log2(mem.size); std::vector data_reg_in(1 << abits); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index a19807f22..6a424952a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -371,9 +371,9 @@ struct MemoryShareWorker ports += std::to_string(idx); } if (!some_port.clk_enable) { - log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports.c_str()); + log(" Checking unclocked group, width %d: ports %s.\n", mem.width << some_port.wide_log2, ports); } else { - log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports.c_str()); + log(" Checking group clocked with %sedge %s, width %d: ports %s.\n", some_port.clk_polarity ? "pos" : "neg", log_signal(some_port.clk), mem.width << some_port.wide_log2, ports); } // Okay, time to actually run the SAT solver. diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 620b38813..4dd5ba616 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -597,7 +597,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit) { if (verbose) - log("Finding unused cells or wires in module %s..\n", module->name.c_str()); + log("Finding unused cells or wires in module %s..\n", module->name); std::vector delcells; for (auto cell : module->cells()) diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 1625b86ea..97147fc48 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -99,7 +99,7 @@ struct OptLutWorker } for (int i = 0; i < GetSize(dlogic); i++) { - log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type.c_str(), i, dlogic_counts[i]); + log(" with %-12s (#%d) %4d\n", dlogic[i].cell_type, i, dlogic_counts[i]); } } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 6c81ee241..fbfdb9b63 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -228,7 +228,7 @@ struct OptMergeWorker ct.cell_types.erase(ID($allseq)); ct.cell_types.erase(ID($allconst)); - log("Finding identical cells in module `%s'.\n", module->name.c_str()); + log("Finding identical cells in module `%s'.\n", module->name); assign_map.set(module); initvals.set(&assign_map, module); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 809353f8c..2f7d26dcf 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -205,7 +205,7 @@ struct OptMuxtreeWorker OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module), removed_count(0) { - log("Running muxtree optimizer on module %s..\n", module->name.c_str()); + log("Running muxtree optimizer on module %s..\n", module->name); log(" Creating internal representation of mux trees.\n"); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d27878fa7..6d6cadfe7 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -93,7 +93,7 @@ struct OptReduceWorker new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1; if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { - log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); + log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a)); did_something = true; total_count++; } @@ -155,7 +155,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size() || (new_sig_s.size() == 1 && cell->type == ID($pmux))) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::B, new_sig_b); @@ -242,7 +242,7 @@ struct OptReduceWorker } if (new_sig_s.size() != sig_s.size()) { - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; cell->setPort(ID::A, new_sig_a); @@ -308,7 +308,7 @@ struct OptReduceWorker if (new_sig_s.size() == sig_s.size() && sig_s.size() > 0) return; - log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); + log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s)); did_something = true; total_count++; @@ -388,7 +388,7 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); if (cell->type != ID($bmux)) { log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); @@ -479,7 +479,7 @@ struct OptReduceWorker if (GetSize(swizzle) != width) { - log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); + log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name); log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::Y))); @@ -515,7 +515,7 @@ struct OptReduceWorker OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) : design(design), module(module), assign_map(module) { - log(" Optimizing cells in module %s.\n", module->name.c_str()); + log(" Optimizing cells in module %s.\n", module->name); total_count = 0; did_something = true; diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 0ac391790..3a39570b4 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -64,7 +64,7 @@ struct RmportsPassPass : public Pass { void CleanupModule(Module *module, dict> &removed_ports) { - log("Removing now-unused cell ports in module %s\n", module->name.c_str()); + log("Removing now-unused cell ports in module %s\n", module->name); auto cells = module->cells(); for(auto cell : cells) @@ -88,7 +88,7 @@ struct RmportsPassPass : public Pass { void ScanModule(Module* module, dict> &removed_ports) { - log("Finding unconnected ports in module %s\n", module->name.c_str()); + log("Finding unconnected ports in module %s\n", module->name); pool used_ports; @@ -113,7 +113,7 @@ struct RmportsPassPass : public Pass { if( (w1 == NULL) || (w2 == NULL) ) continue; - //log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str()); + //log(" conn %s, %s\n", w1->name, w2->name); if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) ) used_ports.insert(w1->name); @@ -136,7 +136,7 @@ struct RmportsPassPass : public Pass { if(sig == NULL) continue; - // log(" sig %s\n", sig->name.c_str()); + // log(" sig %s\n", sig->name); if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) ) used_ports.insert(sig->name); } @@ -155,7 +155,7 @@ struct RmportsPassPass : public Pass { // Print the ports out as we go through them for(auto port : unused_ports) { - log(" removing unused port %s\n", port.c_str()); + log(" removing unused port %s\n", port); removed_ports[module->name].insert(port); // Remove from ports list diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 97c6f5600..d2adbbdd9 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -454,7 +454,7 @@ with open(outfile, "w") as f: print(" SigSpec port(Cell *cell, IdString portname) {", file=f) print(" try {", file=f) print(" return sigmap(cell->getPort(portname));", file=f) - print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname.c_str()); }", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f) print(" }", file=f) print("", file=f) print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f) @@ -465,7 +465,7 @@ with open(outfile, "w") as f: print(" Const param(Cell *cell, IdString paramname) {", file=f) print(" try {", file=f) print(" return cell->getParam(paramname);", file=f) - print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname.c_str()); }", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname); }", file=f) print(" }", file=f) print("", file=f) print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f) diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 3cd3f6fe4..92d8d0569 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -204,7 +204,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { if (edge_syncs.size() > 1) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; arst_syncs.push_back(sync); edge_syncs.erase(it); @@ -223,7 +223,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) sync->mem_write_actions.clear(); eliminate_const(mod, &proc->root_case, root_sig, polarity); } else { - log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str()); + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); eliminate_const(mod, &proc->root_case, root_sig, !polarity); } did_something = true; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index b8bd74f50..19c2be4ca 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -171,7 +171,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool proc_clean_case(&proc->root_case, did_something, count, -1); } if (count > 0 && !quiet) - log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str()); + log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name, proc->name); total_count += count; } @@ -215,7 +215,7 @@ struct ProcCleanPass : public Pass { if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 && proc->root_case.actions.size() == 0) { if (!quiet) - log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str()); + log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name); delme.push_back(proc); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 7e3c56552..06c740a88 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -106,7 +106,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set cell->setPort(ID::CLK, clk); cell->setPort(ID::ALOAD, set); - log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), + log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name, clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); } @@ -136,9 +136,9 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT cell->setPort(ID::CLK, clk); if (!clk.empty()) - log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); + log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative"); else - log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str()); + log(" created %s cell `%s' with global clock", cell->type, cell->name); if (arst) log(" and %s level reset", arst_polarity ? "positive" : "negative"); log(".\n"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index f170dbf36..bda2d272f 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -404,7 +404,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) for (auto &bit : lhs) { State val = db.initvals(bit); if (db.initvals(bit) != State::Sx) { - log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str()); + log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name, log_signal(bit), db.module->name, proc->name); } db.initvals.remove_init(bit); } diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 817ced404..99cacf5fd 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -31,7 +31,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) for (auto &sync : proc->syncs) if (sync->type == RTLIL::SyncType::STi) { - log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str()); + log("Found init rule in `%s.%s'.\n", mod->name, proc->name); for (auto &action : sync->actions) { diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 21afdf134..68127d1bc 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -412,7 +412,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) { - log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str()); + log("Creating decoders for process `%s.%s'.\n", mod->name, proc->name); SigSnippets sigsnip; sigsnip.insert(&proc->root_case); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 7008e35e1..bde5e1ecb 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -87,7 +87,7 @@ struct BruteForceEquivChecker BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) : mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1) { - log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str()); + log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name, mod2->name); for (auto w : mod1->wires()) { if (w->port_id == 0) @@ -264,7 +264,7 @@ struct VlogHammerReporter if (!ce.eval(sig)) log_error("Can't read back value for port %s!\n", log_id(inputs[i])); input_pattern_list += stringf(" %s", sig.as_const().as_string()); - log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str()); + log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string()); } } @@ -280,7 +280,7 @@ struct VlogHammerReporter ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size())); } - log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); + log("++VAL++ %d %s %s #\n", idx, module_name, sig.as_const().as_string()); if (module_name == "rtl") { rtl_sig = sig; @@ -294,7 +294,7 @@ struct VlogHammerReporter sig[i] = RTLIL::State::Sx; } - log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str()); + log("++RPT++ %d%s %s %s\n", idx, input_pattern_list, sig.as_const().as_string(), module_name); } log("++RPT++ ----\n"); @@ -307,8 +307,8 @@ struct VlogHammerReporter for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); if (design->module(esc_name) == nullptr) - log_error("Can't find module %s in current design!\n", name.c_str()); - log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); + log_error("Can't find module %s in current design!\n", name); + log("Using module %s (%s).\n", esc_name, name); modules.push_back(design->module(esc_name)); module_names.push_back(name); } @@ -319,15 +319,15 @@ struct VlogHammerReporter RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { if (mod->wire(esc_name) == nullptr) - log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name)); + log_error("Can't find input %s in module %s!\n", name, log_id(mod->name)); RTLIL::Wire *port = mod->wire(esc_name); if (!port->port_input || port->port_output) - log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name)); + log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name)); if (width >= 0 && width != port->width) - log_error("Port %s has different sizes in the different modules!\n", name.c_str()); + log_error("Port %s has different sizes in the different modules!\n", name); width = port->width; } - log("Using input port %s with width %d.\n", esc_name.c_str(), width); + log("Using input port %s with width %d.\n", esc_name, width); inputs.push_back(esc_name); input_widths.push_back(width); total_input_width += width; @@ -341,9 +341,9 @@ struct VlogHammerReporter pattern = pattern.substr(1); } if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const()) - log_error("Failed to parse pattern %s!\n", pattern.c_str()); + log_error("Failed to parse pattern %s!\n", pattern); if (sig.size() < total_input_width) - log_error("Pattern %s is to short!\n", pattern.c_str()); + log_error("Pattern %s is to short!\n", pattern); patterns.push_back(sig.as_const()); if (invert_pattern) { for (auto &bit : patterns.back().bits()) @@ -352,7 +352,7 @@ struct VlogHammerReporter else if (bit == RTLIL::State::S1) bit = RTLIL::State::S0; } - log("Using pattern %s.\n", patterns.back().as_string().c_str()); + log("Using pattern %s.\n", patterns.back().as_string()); } } }; @@ -415,9 +415,9 @@ struct EvalPass : public Pass { std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); if (design->module(mod1_name) == nullptr) - log_error("Can't find module `%s'!\n", mod1_name.c_str()); + log_error("Can't find module `%s'!\n", mod1_name); if (design->module(mod2_name) == nullptr) - log_error("Can't find module `%s'!\n", mod2_name.c_str()); + log_error("Can't find module `%s'!\n", mod2_name); BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivalent!\n"); @@ -574,7 +574,7 @@ struct EvalPass : public Pass { for (auto &row : tab) { for (size_t i = 0; i < row.size(); i++) { int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i; - log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str()); + log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k]); } log("\n"); if (first) { diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 547082164..4627a6c96 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -109,7 +109,7 @@ struct FminitPass : public Pass { SigSpec clksig; if (!clocksignal.empty()) { if (!SigSpec::parse(clksig, module, clocksignal)) - log_error("Error parsing expression '%s'.\n", clocksignal.c_str()); + log_error("Error parsing expression '%s'.\n", clocksignal); } for (auto &it : setdata) @@ -117,10 +117,10 @@ struct FminitPass : public Pass { SigSpec lhs, rhs; if (!SigSpec::parse(lhs, module, it.first)) - log_error("Error parsing expression '%s'.\n", it.first.c_str()); + log_error("Error parsing expression '%s'.\n", it.first); if (!SigSpec::parse_rhs(lhs, rhs, module, it.second)) - log_error("Error parsing expression '%s'.\n", it.second.c_str()); + log_error("Error parsing expression '%s'.\n", it.second); SigSpec final_lhs, final_rhs; @@ -144,7 +144,7 @@ struct FminitPass : public Pass { SigSpec lhs, rhs; if (!SigSpec::parse(lhs, module, it.first)) - log_error("Error parsing expression '%s'.\n", it.first.c_str()); + log_error("Error parsing expression '%s'.\n", it.first); for (int i = 0; i < GetSize(it.second); i++) { @@ -183,7 +183,7 @@ struct FminitPass : public Pass { SigSpec final_lhs, final_rhs; if (!SigSpec::parse_rhs(lhs, rhs, module, it.second[i])) - log_error("Error parsing expression '%s'.\n", it.second[i].c_str()); + log_error("Error parsing expression '%s'.\n", it.second[i]); for (int i = 0; i < GetSize(rhs); i++) if (rhs[i] != State::Sz) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 870df7b55..4b0669c25 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -247,7 +247,7 @@ struct PerformReduction string loop_signals; for (auto loop_bit : recursion_guard) loop_signals += string(" ") + log_signal(loop_bit); - log_error("Found logic loop:%s\n", loop_signals.c_str()); + log_error("Found logic loop:%s\n", loop_signals); } recursion_guard.insert(out); @@ -596,7 +596,7 @@ struct FreduceWorker void dump() { std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter); - log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str()); + log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); } diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 7aef9ea38..58d932f20 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -539,7 +539,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena std::ofstream sout; sout.open(srcsfile, std::ios::out | std::ios::trunc); if (!sout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str()); + log_error("Could not open file \"%s\" with write access.\n", srcsfile); sources.sort(); for (auto &s : sources) sout << s << std::endl; @@ -550,7 +550,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena if (!filename.empty()) { fout.open(filename, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", filename.c_str()); + log_error("Could not open file \"%s\" with write access.\n", filename); } int ctrl_value = opts.ctrl_value; @@ -561,7 +561,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++); str += " -mode none"; if (filename.empty()) - log("%s\n", str.c_str()); + log("%s\n", str); else fout << str << std::endl; } @@ -588,7 +588,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena for (auto &s : entry.src) str += stringf(" -src %s", s); if (filename.empty()) - log("%s\n", str.c_str()); + log("%s\n", str); else fout << str << std::endl; } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index c7ddb9168..20cee7956 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -122,7 +122,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { for (auto &it : hole_assignments) { RTLIL::SigSpec lhs(it.first); RTLIL::SigSpec rhs(it.second); - log("Specializing %s from file with %s = %d.\n", module->name.c_str(), log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0); + log("Specializing %s from file with %s = %d.\n", module->name, log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0); module->connect(lhs, rhs); } } @@ -151,7 +151,7 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet = RTLIL::SigSpec lhs(hole_sigbit.wire, hole_sigbit.offset, 1); RTLIL::State hole_bit_val = hole_value[bit_idx] == '1'? RTLIL::State::S1 : RTLIL::State::S0; if (!quiet) - log("Specializing %s with %s = %d.\n", module->name.c_str(), log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1) + log("Specializing %s with %s = %d.\n", module->name, log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1) ; module->connect(lhs, hole_bit_val); } @@ -168,7 +168,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool &input_wi allconst->setPort(ID::Y, input); allconst->set_src_attribute(input->get_src_attribute()); input->port_input = false; - log("Replaced input %s with $allconst cell.\n", n.c_str()); + log("Replaced input %s with $allconst cell.\n", n); } module->fixup_ports(); } @@ -184,7 +184,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) { else { log("Adding $assume cell for output(s): "); for (auto w : wires_to_assume) - log("\"%s\" ", w->name.c_str()); + log("\"%s\" ", w->name); log("\n"); } @@ -236,10 +236,10 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str()); else if (opt.show_smtbmc && !quiet) - log("smtbmc output: %s", line.c_str()); + log("smtbmc output: %s", line); }; log_header(mod->design, "Solving QBF-SAT problem.\n"); - if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd.c_str()); + if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd); int64_t begin = PerformanceTimer::query(); run_command(smtbmc_cmd, process_line); int64_t end = PerformanceTimer::query(); @@ -303,7 +303,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { log_assert(wire_to_optimize_name != ""); log_assert(module->wire(wire_to_optimize_name) != nullptr); - log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name.c_str()); + log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name); //If maximizing, grow until we get a failure. Then bisect success and failure. while (failure == 0 || difference(success, failure) > 1) { @@ -316,7 +316,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { : module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1)); - log("Trying to solve with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), cur_thresh); + log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh); } ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num); @@ -337,7 +337,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { log_assert(value.is_fully_const()); success = value.as_const().as_int(); best_soln = ret; - log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name.c_str(), success); + log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name, success); Pass::call(design, "design -pop"); module = design->module(module_name); @@ -355,7 +355,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { break; } else - log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), failure); + log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), failure); } iter_num++; @@ -367,7 +367,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { cur_thresh = (success + failure) / 2; //bisection } if (success != 0 || failure != 0) { - log("Wire %s is %s at %d.\n", wire_to_optimize_name.c_str(), (maximize? "maximized" : "minimized"), success); + log("Wire %s is %s at %d.\n", wire_to_optimize_name, (maximize? "maximized" : "minimized"), success); ret = best_soln; } } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 60e099097..967cb0472 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -652,9 +652,9 @@ struct SatHelper log(" "); if (info.width <= 32 && !found_undef) - log("%-*s %11d %9x %*s\n", maxModelName+5, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+3, value.as_string().c_str()); + log("%-*s %11d %9x %*s\n", maxModelName+5, info.description, value.as_int(), value.as_int(), maxModelWidth+3, value.as_string()); else - log("%-*s %11s %9s %*s\n", maxModelName+5, info.description.c_str(), "--", "--", maxModelWidth+3, value.as_string().c_str()); + log("%-*s %11s %9s %*s\n", maxModelName+5, info.description, "--", "--", maxModelWidth+3, value.as_string()); } if (last_timestep == -2) @@ -668,7 +668,7 @@ struct SatHelper if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); - log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str()); + log("Dumping SAT model to VCD file %s\n", vcd_file_name); time_t timestamp; struct tm* now; @@ -772,7 +772,7 @@ struct SatHelper if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno)); - log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name.c_str()); + log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name); int mintime = 1, maxtime = 0, maxwidth = 0;; dict>> wavedata; @@ -1530,7 +1530,7 @@ struct SatPass : public Pass { if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); - log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); inductstep.ez->printDIMACS(f, false); @@ -1634,7 +1634,7 @@ struct SatPass : public Pass { if (!f) log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); - log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str()); + log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); sathelper.ez->printDIMACS(f, false); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 044bd8acb..0510bc7df 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -60,10 +60,10 @@ static double stringToTime(std::string str) long value = strtol(str.c_str(), &endptr, 10); if (g_units.find(endptr)==g_units.end()) - log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr); + log_error("Cannot parse '%s', bad unit '%s'\n", str, endptr); if (value < 0) - log_error("Time value '%s' must be positive\n", str.c_str()); + log_error("Time value '%s' must be positive\n", str); return value * pow(10.0, g_units.at(endptr)); } @@ -430,7 +430,7 @@ struct SimInstance value.bits().push_back(State::Sz); if (shared->debug) - log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); return value; } @@ -449,7 +449,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value)); return did_something; } @@ -551,7 +551,7 @@ struct SimInstance if (has_y) sig_y = cell->getPort(ID::Y); if (shared->debug) - log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type)); + log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type)); // Simple (A -> Y) and (A,B -> Y) cells if (has_a && !has_c && !has_d && !has_s && has_y) { @@ -793,14 +793,14 @@ struct SimInstance static void log_source(RTLIL::AttrObject *src) { for (auto src : src->get_strpool_attribute(ID::src)) - log(" %s\n", src.c_str()); + log(" %s\n", src); } void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell) { log_assert(cell->module == module); bool has_src = cell->has_attribute(ID::src); - log("%s %s%s\n", opening_verbiage.c_str(), + log("%s %s%s\n", opening_verbiage, log_id(cell), has_src ? " at" : ""); log_source(cell); @@ -894,7 +894,7 @@ struct SimInstance } std::string rendered = print.fmt.render(); - log("%s", rendered.c_str()); + log("%s", rendered); shared->display_output.emplace_back(shared->step, this, cell, rendered); } } @@ -921,15 +921,15 @@ struct SimInstance } if (cell->type == ID($cover) && en == State::S1 && a == State::S1) - log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str()); + log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label); if (cell->type == ID($assume) && en == State::S1 && a != State::S1) - log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label); if (cell->type == ID($assert) && en == State::S1 && a != State::S1) { log_cell_w_hierarchy("Failed assertion", cell); if (shared->serious_asserts) - log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label); else log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); } @@ -952,7 +952,7 @@ struct SimInstance { if (!ff_database.empty() || !mem_database.empty()) { if (wbmods.count(module)) - log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module)); + log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module)); wbmods.insert(module); } @@ -1192,7 +1192,7 @@ struct SimInstance } } if (!found) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name))); } } } @@ -1478,7 +1478,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); } for (auto portname : clockn) @@ -1490,7 +1490,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); } @@ -1500,7 +1500,7 @@ struct SimWorker : SimShared if (wire->port_input) { fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); top->fst_inputs[wire] = id; } } @@ -1623,9 +1623,9 @@ struct SimWorker : SimShared else if (type == "latch") mem_latches[variable] = { memid, offset }; else - log_error("Map file addressing cell %s as type %s\n", symbol.c_str(), type.c_str()); + log_error("Map file addressing cell %s as type %s\n", symbol, type); } else { - log_error("Cell %s in map file is not memory cell\n", symbol.c_str()); + log_error("Cell %s in map file is not memory cell\n", symbol); } } else { if (index < w->start_offset || index > w->start_offset + w->width) @@ -1645,7 +1645,7 @@ struct SimWorker : SimShared std::ifstream f; f.open(sim_filename.c_str()); if (f.fail() || GetSize(sim_filename) == 0) - log_error("Can not open file `%s`\n", sim_filename.c_str()); + log_error("Can not open file `%s`\n", sim_filename); int state = 0; std::string status; @@ -1729,7 +1729,7 @@ struct SimWorker : SimShared if (pos==std::string::npos) { pos = name.find_first_of("#"); if (pos==std::string::npos) - log_error("Line does not contain proper signal name `%s`\n", name.c_str()); + log_error("Line does not contain proper signal name `%s`\n", name); } return name.substr(0, pos); } @@ -1744,7 +1744,7 @@ struct SimWorker : SimShared std::ifstream f; f.open(sim_filename.c_str()); if (f.fail() || GetSize(sim_filename) == 0) - log_error("Can not open file `%s`\n", sim_filename.c_str()); + log_error("Can not open file `%s`\n", sim_filename); int state = 0; int cycle = 0; @@ -1874,7 +1874,7 @@ struct SimWorker : SimShared if (item.wire != nullptr) { if (paths.count(path)) { if (debug) - log("witness hierarchy: found wire %s\n", path.str().c_str()); + log("witness hierarchy: found wire %s\n", path.str()); bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second; if (!inserted) log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str()); @@ -1883,7 +1883,7 @@ struct SimWorker : SimShared auto it = mem_paths.find(path); if (it != mem_paths.end()) { if (debug) - log("witness hierarchy: found mem %s\n", path.str().c_str()); + log("witness hierarchy: found mem %s\n", path.str()); IdPath word_path = path; word_path.emplace_back(); for (auto addr_part : it->second) { @@ -1951,7 +1951,7 @@ struct SimWorker : SimShared Const value = yw.get_bits(t, signal.bits_offset, signal.width); if (debug) - log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value)); + log("yw: set %s to %s\n", signal.path.str(), log_const(value)); if (found_path.wire != nullptr) { found_path.instance->set_state_parent_drivers( @@ -2052,7 +2052,7 @@ struct SimWorker : SimShared PrettyJson json; if (!json.write_to_file(summary_filename)) - log_error("Can't open file `%s' for writing: %s\n", summary_filename.c_str(), strerror(errno)); + log_error("Can't open file `%s' for writing: %s\n", summary_filename, strerror(errno)); json.begin_object(); json.entry("version", "Yosys sim summary"); @@ -2134,7 +2134,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); clocks[w] = id; } @@ -2147,7 +2147,7 @@ struct SimWorker : SimShared log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname)); if (id==0) - log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname)); + log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname)); fst_clock.push_back(id); clocks[w] = id; } @@ -2159,7 +2159,7 @@ struct SimWorker : SimShared for (auto wire : topmod->wires()) { fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); if (id==0 && (wire->port_input || wire->port_output)) - log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); + log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name))); if (wire->port_input) if (clocks.find(wire)==clocks.end()) inputs[wire] = id; @@ -2236,7 +2236,7 @@ struct SimWorker : SimShared f << "\n"; f << "\tinteger i;\n"; uint64_t prev_time = startCount; - log("Writing data to `%s`\n", (tb_filename+".txt").c_str()); + log("Writing data to `%s`\n", (tb_filename+".txt")); std::ofstream data_file(tb_filename+".txt"); std::stringstream initstate; unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX; @@ -2292,7 +2292,7 @@ struct SimWorker : SimShared f << "\tend\n"; f << "endmodule\n"; - log("Writing testbench to `%s`\n", (tb_filename+".v").c_str()); + log("Writing testbench to `%s`\n", (tb_filename+".v")); std::ofstream tb_file(tb_filename+".v"); tb_file << f.str(); diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 4703e4ad7..d94b4a7f7 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -170,7 +170,7 @@ void SynthPropWorker::run() std::ofstream fout; fout.open(map_file, std::ios::out | std::ios::trunc); if (!fout.is_open()) - log_error("Could not open file \"%s\" with write access.\n", map_file.c_str()); + log_error("Could not open file \"%s\" with write access.\n", map_file); for (auto name : tracing_data[module].names) { fout << name << std::endl; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index d45a652fc..7d81b52d2 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -751,7 +751,7 @@ struct abc_output_filter return; } if (ch == '\n') { - log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str()); + log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -936,7 +936,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab std::string buffer = stringf("%s/abc.script", tempdir_name); FILE *f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, "%s\n", abc_script.c_str()); fclose(f); @@ -991,7 +991,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/input.blif", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, ".model netlist\n"); @@ -1118,7 +1118,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/stdcells.genlib", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); fprintf(f, "GATE ONE 1 Y=CONST1;\n"); fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_))); @@ -1163,14 +1163,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == nullptr) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); for (int i = 0; i < GetSize(config.lut_costs); i++) fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i)); fclose(f); } buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name); - log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str()); + log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir)); #ifndef YOSYS_LINK_ABC abc_output_filter filt(*this, tempdir_name, config.show_tempdir); @@ -1220,7 +1220,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab temp_stdouterr_r.close(); #endif if (ret != 0) { - log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); return; } did_run_abc = true; @@ -1239,7 +1239,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL std::ifstream ifs; ifs.open(buffer); if (ifs.fail()) - log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); + log_error("Can't open ABC output file `%s'.\n", buffer); bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; @@ -1490,7 +1490,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL cell_stats.sort(); for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); + log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second); int in_wires = 0, out_wires = 0; for (auto &si : signal_list) if (si.is_port) { @@ -1582,7 +1582,7 @@ struct AbcPass : public Pass { #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -1597,41 +1597,41 @@ struct AbcPass : public Pass { log(" if no -script parameter is given, the following scripts are used:\n"); log("\n"); log(" for -liberty/-genlib without -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB)); log("\n"); log(" for -liberty/-genlib with -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR)); log("\n"); log(" for -lut/-luts (only one LUT size):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}")); log("\n"); log(" for -lut/-luts (different LUT sizes):\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT)); log("\n"); log(" for -sop:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP)); log("\n"); log(" otherwise:\n"); - log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str()); + log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL)); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); log("\n"); log(" for -liberty/-genlib without -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB)); log("\n"); log(" for -liberty/-genlib with -constr:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR)); log("\n"); log(" for -lut/-luts:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT)); log("\n"); log(" for -sop:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP)); log("\n"); log(" otherwise:\n"); - log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str()); + log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL)); log("\n"); log(" -liberty \n"); log(" generate netlists for the specified cell library (using the liberty\n"); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b79d9dc96..2cf28f849 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -106,7 +106,7 @@ struct Abc9Pass : public ScriptPass #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -119,12 +119,12 @@ struct Abc9Pass : public ScriptPass log(" replaced with blanks before the string is passed to ABC.\n"); log("\n"); log(" if no -script parameter is given, the following scripts are used:\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos))); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos))); log("\n"); log(" -D \n"); log(" set delay target. the string {D} in the default scripts above is\n"); diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 34348fd00..d7a7e3d4a 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -140,7 +140,7 @@ struct abc9_output_filter return; } if (ch == '\n') { - log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str()); + log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir)); got_cr = false, linebuf.clear(); return; } @@ -271,14 +271,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe buffer = stringf("%s/lutdefs.txt", tempdir_name); f = fopen(buffer.c_str(), "wt"); if (f == NULL) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); + log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno)); for (int i = 0; i < GetSize(lut_costs); i++) fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i)); fclose(f); } buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name); - log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); + log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir)); #ifndef YOSYS_LINK_ABC abc9_output_filter filt(tempdir_name, show_tempdir); @@ -331,7 +331,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe if (check_file_exists(stringf("%s/output.aig", tempdir_name))) log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); else - log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); + log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret); } } @@ -352,7 +352,7 @@ struct Abc9ExePass : public Pass { #ifdef ABCEXTERNAL log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n"); #else - log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str()); + log(" use the specified command instead of \"/%syosys-abc\" to execute ABC.\n", proc_program_prefix()); #endif log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n"); log("\n"); @@ -365,12 +365,12 @@ struct Abc9ExePass : public Pass { log(" replaced with blanks before the string is passed to ABC.\n"); log("\n"); log(" if no -script parameter is given, the following scripts are used:\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos))); log("\n"); log(" -fast\n"); log(" use different default scripts that are slightly faster (at the cost\n"); log(" of output quality):\n"); - log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str()); + log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos))); log("\n"); log(" -constr \n"); log(" pass this file with timing constraints to ABC.\n"); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 85a1099ed..91149ac55 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -787,7 +787,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (auto cell_name : it) { auto cell = module->cell(cell_name); log_assert(cell); - log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str()); + log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute()); } } } @@ -1444,7 +1444,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) } for (auto &it : cell_stats) - log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); + log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second); int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 7f5bfc94f..58ac25f51 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -130,14 +130,14 @@ void attrmap_apply(string objname, vector> &actio goto delete_this_attr; if (new_attr != attr) - log("Changed attribute on %s: %s=%s -> %s=%s\n", objname.c_str(), + log("Changed attribute on %s: %s=%s -> %s=%s\n", objname, log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second)); new_attributes[new_attr.first] = new_attr.second; if (0) delete_this_attr: - log("Removed attribute on %s: %s=%s\n", objname.c_str(), log_id(attr.first), log_const(attr.second)); + log("Removed attribute on %s: %s=%s\n", objname, log_id(attr.first), log_const(attr.second)); } attributes.swap(new_attributes); diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index a7b96a9c6..7003c6656 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -257,14 +257,14 @@ struct ClkbufmapPass : public Pass { RTLIL::Cell *cell = nullptr; bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top); if (!buf_celltype.empty() && (!is_input || buffer_inputs)) { - log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i); + log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i); cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype)); iwire = module->addWire(NEW_ID); cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit); cell->setPort(RTLIL::escape_id(buf_portname2), iwire); } if (is_input) { - log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i); + log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i); RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype)); if (iwire) { cell2->setPort(RTLIL::escape_id(inpad_portname), iwire); diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 508e66d23..b834b8f35 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -81,7 +81,7 @@ static std::pair, std::optional> } else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) { clk_pol = false; } else { - log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str()); + log("Ignoring ICG primitive %s of kind '%s'\n", cell_name, icg_kind); continue; } @@ -176,11 +176,11 @@ static std::pair, std::optional> std::optional pos; std::optional neg; if (best_pos) { - log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str()); + log("Selected rising edge ICG %s from Liberty file\n", best_pos->name); pos.emplace(*best_pos); } if (best_neg) { - log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str()); + log("Selected falling edge ICG %s from Liberty file\n", best_neg->name); neg.emplace(*best_neg); } return std::make_pair(pos, neg); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 9dfc20896..facea2e90 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1111,7 +1111,7 @@ struct DffLegalizePass : public Pass { pol_r = celltype[13]; } else { unrecognized: - log_error("unrecognized cell type %s.\n", celltype.c_str()); + log_error("unrecognized cell type %s.\n", celltype); } int mask = 0; int match = 0; @@ -1140,12 +1140,12 @@ unrecognized: initmask = 0x555; } else if (inittype == "r") { if (srval == 0) - log_error("init type r not valid for cell type %s.\n", celltype.c_str()); + log_error("init type r not valid for cell type %s.\n", celltype); initmask = 0x537; } else if (inittype == "01") { initmask = 0x777; } else { - log_error("unrecognized init type %s for cell type %s.\n", inittype.c_str(), celltype.c_str()); + log_error("unrecognized init type %s for cell type %s.\n", inittype, celltype); } if (srval == '0') { initmask &= 0x0ff; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 70d0f4ef5..062a63ec3 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -36,9 +36,9 @@ static std::map cell_mappings; static void logmap(IdString dff) { if (cell_mappings.count(dff) == 0) { - log(" unmapped dff cell: %s\n", dff.c_str()); + log(" unmapped dff cell: %s\n", dff); } else { - log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str()); + log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1)); bool first = true; for (auto &port : cell_mappings[dff].ports) { char arg[3] = { port.second, 0, 0 }; @@ -46,7 +46,7 @@ static void logmap(IdString dff) arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~'; else arg[1] = arg[0], arg[0] = ' '; - log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg); + log("%s.%s(%s)", first ? "" : ", ", port.first, arg); first = false; } log(");\n"); @@ -488,7 +488,7 @@ static void find_cell_sr(std::vector cells, IdString cell_ty static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) { - log("Mapping DFF cells in module `%s':\n", module->name.c_str()); + log("Mapping DFF cells in module `%s':\n", module->name); dict> notmap; SigMap sigmap(module); @@ -690,7 +690,7 @@ struct DfflibmapPass : public Pass { dfflegalize_cmd += stringf(" -cell %s 01", it.first); dfflegalize_cmd += " t:$_DFF* t:$_SDFF*"; if (info_mode) { - log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str()); + log("dfflegalize command line: %s\n", dfflegalize_cmd); } else { Pass::call(design, dfflegalize_cmd); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index ea6ba5ddb..6527b683e 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -627,7 +627,7 @@ struct ExtractPass : public Pass { for (auto module : map->modules()) { SubCircuit::Graph mod_graph; std::string graph_name = "needle_" + RTLIL::unescape_id(module->name); - log("Creating needle graph %s.\n", graph_name.c_str()); + log("Creating needle graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports)) { solver.addGraph(graph_name, mod_graph); needle_map[graph_name] = module; @@ -638,7 +638,7 @@ struct ExtractPass : public Pass { for (auto module : design->modules()) { SubCircuit::Graph mod_graph; std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name); - log("Creating haystack graph %s.\n", graph_name.c_str()); + log("Creating haystack graph %s.\n", graph_name); if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) { solver.addGraph(graph_name, mod_graph); haystack_map[graph_name] = module; @@ -654,7 +654,7 @@ struct ExtractPass : public Pass { for (auto needle : needle_list) for (auto &haystack_it : haystack_map) { - log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str()); + log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first); solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false); } log("Found %d matches.\n", GetSize(results)); @@ -665,11 +665,11 @@ struct ExtractPass : public Pass { for (int i = 0; i < int(results.size()); i++) { auto &result = results[i]; - log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str()); + log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId, result.haystackGraphId); for (const auto &it : result.mappings) { - log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str()); + log(" %s -> %s", it.first, it.second.haystackNodeId); for (const auto & it2 : it.second.portMapping) - log(" %s:%s", it2.first.c_str(), it2.second.c_str()); + log(" %s:%s", it2.first, it2.second); log("\n"); } RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result); @@ -693,7 +693,7 @@ struct ExtractPass : public Pass { log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits); log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name)); for (auto &node : result.nodes) - log(" %s", RTLIL::unescape_id(node.nodeId).c_str()); + log(" %s", RTLIL::unescape_id(node.nodeId)); log("\n"); for (auto &it : result.matchesPerGraph) log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second); @@ -744,7 +744,7 @@ struct ExtractPass : public Pass { rewrite_filename(mine_outfile); f.open(mine_outfile.c_str(), std::ofstream::trunc); if (f.fail()) - log_error("Can't open output file `%s'.\n", mine_outfile.c_str()); + log_error("Can't open output file `%s'.\n", mine_outfile); Backend::backend_call(map, &f, mine_outfile, "rtlil"); f.close(); } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index b780f7df0..c45792f66 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -847,7 +847,7 @@ struct ExtractCounterPass : public Pass { else if (arg == "no") settings.allow_arst = false; else - log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str()); + log_error("Invalid -allow_arst value \"%s\"\n", arg); continue; } @@ -861,7 +861,7 @@ struct ExtractCounterPass : public Pass { else if (arg == "both") settings.allowed_dirs = 2; else - log_error("Invalid -dir value \"%s\"\n", arg.c_str()); + log_error("Invalid -dir value \"%s\"\n", arg); continue; } } @@ -893,7 +893,7 @@ struct ExtractCounterPass : public Pass { for(auto cpair : cells_to_rename) { - //log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second.c_str()); + //log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second); module->rename(cpair.first, cpair.second); } } diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 892e9a364..1ad880be0 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -133,7 +133,7 @@ struct ExtractReducePass : public Pass else continue; - log("Working on cell %s...\n", cell->name.c_str()); + log("Working on cell %s...\n", cell->name); // If looking for a single chain, follow linearly to the sink pool sinks; @@ -220,7 +220,7 @@ struct ExtractReducePass : public Pass //We have our list, go act on it for(auto head_cell : sinks) { - log(" Head cell is %s\n", head_cell->name.c_str()); + log(" Head cell is %s\n", head_cell->name); //Avoid duplication if we already were covered if(consumed_cells.count(head_cell)) diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 48d9600fa..5050e1464 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass { RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype)); icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i)); icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]); - log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i); + log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i); sig[i] = SigBit(iwire, i); } cell->setPort(port.first, sig); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 61966195c..7fbe54849 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -598,7 +598,7 @@ struct FlowmapWorker continue; if (!cell->known()) - log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell)); + log_error("Cell %s (%s.%s) is unknown.\n", cell->type, log_id(module), log_id(cell)); pool fanout; for (auto conn : cell->connections()) diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 322eb7779..d929de300 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -324,7 +324,7 @@ struct IopadmapPass : public Pass { if (wire->port_input) { - log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str()); + log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype); Cell *cell = module->addCell( module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), @@ -348,7 +348,7 @@ struct IopadmapPass : public Pass { if (!tinoutpad_portname_pad.empty()) rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad)); } else { - log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str()); + log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype); Cell *cell = module->addCell( module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)), @@ -421,7 +421,7 @@ struct IopadmapPass : public Pass { continue; } - log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); + log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype); if (flag_bits) { diff --git a/passes/techmap/libcache.cc b/passes/techmap/libcache.cc index e299f43ec..c833a6046 100644 --- a/passes/techmap/libcache.cc +++ b/passes/techmap/libcache.cc @@ -117,9 +117,9 @@ if (list) { log("Caching is %s by default.\n", LibertyAstCache::instance.cache_by_default ? "enabled" : "disabled"); for (auto const &entry : LibertyAstCache::instance.cache_path) - log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first.c_str()); + log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first); for (auto const &entry : LibertyAstCache::instance.cached) - log("Data for `%s' is currently cached.\n", entry.first.c_str()); + log("Data for `%s' is currently cached.\n", entry.first); } else if (enable || disable) { if (all) { LibertyAstCache::instance.cache_by_default = enable; diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index b60e0b84b..c89495c62 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -42,7 +42,7 @@ std::shared_ptr LibertyAstCache::cached_ast(const std::string if (it == cached.end()) return nullptr; if (verbose) - log("Using cached data for liberty file `%s'\n", fname.c_str()); + log("Using cached data for liberty file `%s'\n", fname); return it->second; } @@ -53,7 +53,7 @@ void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr if (!should_cache) return; if (verbose) - log("Caching data for liberty file `%s'\n", fname.c_str()); + log("Caching data for liberty file `%s'\n", fname); cached.emplace(fname, ast); } @@ -671,7 +671,7 @@ void LibertyParser::error(const std::string &str) const std::stringstream ss; ss << "Syntax error in liberty file on line " << line << ".\n"; ss << " " << str << "\n"; - log_error("%s", ss.str().c_str()); + log_error("%s", ss.str()); } #else diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index ee0f3db42..44b5d3d47 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -204,7 +204,7 @@ namespace Yosys } ast = shared_ast.get(); if (!ast) { - log_error("No entries found in liberty file `%s'.\n", fname.c_str()); + log_error("No entries found in liberty file `%s'.\n", fname); } } #endif diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index dd82958fa..2a22258b7 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -247,7 +247,7 @@ struct TechmapWorker portname = positional_ports.at(portname); if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) { if (portname.begins_with("$")) - log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str()); + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname, cell->name, tpl->name); continue; } @@ -562,7 +562,7 @@ struct TechmapWorker if (extmapper_name == "wrap") { std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); - log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + log("Running \"%s\" on wrapper %s.\n", cmd_string, log_id(extmapper_module)); mkdebug.on(); Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); log_continue = true; @@ -580,7 +580,7 @@ struct TechmapWorker auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); } @@ -589,7 +589,7 @@ struct TechmapWorker auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); @@ -951,7 +951,7 @@ struct TechmapWorker auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type)); if (!log_msg_cache.count(msg)) { log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + log("%s\n", msg); } log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl)); techmap_module_worker(design, module, cell, tpl); diff --git a/passes/tests/raise_error.cc b/passes/tests/raise_error.cc index 588a40806..7233e78fa 100644 --- a/passes/tests/raise_error.cc +++ b/passes/tests/raise_error.cc @@ -85,7 +85,7 @@ struct RaiseErrorPass : public Pass { if (use_stderr) { std::cerr << err_msg << std::endl; } else { - log_error("%s\n", err_msg.c_str()); + log_error("%s\n", err_msg); } } diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index bcaf097a1..52cb8e28c 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -109,7 +109,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s continue; int count_ports = 0; - log("Generating test bench for module `%s'.\n", mod->name.c_str()); + log("Generating test bench for module `%s'.\n", mod->name); for (auto wire : mod->wires()) { if (wire->port_output) { count_ports++; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index a08a6ec29..286ef757d 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -722,7 +722,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: } if (verbose) - log("EVAL: %s\n", out_val.as_string().c_str()); + log("EVAL: %s\n", out_val.as_string()); if (!nosat) { diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index 50710e2bd..2b2249596 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -298,7 +298,7 @@ struct Coolrunner2FixupPass : public Pass { if ((!sig_fed_by_xor[input] && !sig_fed_by_io[input]) || (sig_fed_by_io[input] && ibuf_out_to_packed_reg_cell[input] != cell)) { - log("Buffering input to \"%s\"\n", cell->name.c_str()); + log("Buffering input to \"%s\"\n", cell->name); auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str()); @@ -320,7 +320,7 @@ struct Coolrunner2FixupPass : public Pass { if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock]) { - log("Buffering clock to \"%s\"\n", cell->name.c_str()); + log("Buffering clock to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, clock); @@ -338,7 +338,7 @@ struct Coolrunner2FixupPass : public Pass { { if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set]) { - log("Buffering set to \"%s\"\n", cell->name.c_str()); + log("Buffering set to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, set); @@ -352,7 +352,7 @@ struct Coolrunner2FixupPass : public Pass { { if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset]) { - log("Buffering reset to \"%s\"\n", cell->name.c_str()); + log("Buffering reset to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, reset); @@ -369,7 +369,7 @@ struct Coolrunner2FixupPass : public Pass { ce = sigmap(cell->getPort(ID(CE))[0]); if (!sig_fed_by_pterm[ce]) { - log("Buffering clock enable to \"%s\"\n", cell->name.c_str()); + log("Buffering clock enable to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, ce); @@ -389,7 +389,7 @@ struct Coolrunner2FixupPass : public Pass { if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) || packed_reg_out[input]) { - log("Buffering input to \"%s\"\n", cell->name.c_str()); + log("Buffering input to \"%s\"\n", cell->name); auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str()); @@ -404,7 +404,7 @@ struct Coolrunner2FixupPass : public Pass { oe = sigmap(cell->getPort(ID::E)[0]); if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe]) { - log("Buffering output enable to \"%s\"\n", cell->name.c_str()); + log("Buffering output enable to \"%s\"\n", cell->name); auto pterm_to_oe_wire = makeptermbuffer(module, oe); diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 955860740..0d07e2522 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -46,12 +46,12 @@ static void run_ice40_braminit(Module *module) continue; /* Open file */ - log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str()); + log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file); std::ifstream f; f.open(init_file.c_str()); if (f.fail()) { - log("Can not open file `%s`.\n", init_file.c_str()); + log("Can not open file `%s`.\n", init_file); continue; } diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index cbd05cb3e..8a13c4325 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -294,7 +294,7 @@ struct MicrochipDffOptPass : public Pass { ports += " + S"; if (worthy_post_ce) ports += " + CE"; - log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); // Okay, we're doing it. Unmap ports. diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index edd906048..bca3deef9 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -305,7 +305,7 @@ unmap: if (worthy_post_r) ports += " + R"; if (worthy_post_s) ports += " + S"; if (worthy_post_ce) ports += " + CE"; - log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports, log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); // Okay, we're doing it. Unmap ports. if (worthy_post_r) {