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Remove .c_str() calls from log()/log_error()

Browse source 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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42
passes/techmap/abc.cc
View file

@ -751,7 +751,7 @@ struct abc_output_filter
return;
}
if (ch == '\n') {
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
got_cr = false, linebuf.clear();
return;
}
@ -936,7 +936,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
std::string buffer = stringf("%s/abc.script", tempdir_name);
FILE *f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, "%s\n", abc_script.c_str());
fclose(f);
@ -991,7 +991,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/input.blif", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, ".model netlist\n");
@ -1118,7 +1118,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/stdcells.genlib", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
@ -1163,14 +1163,14 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == nullptr)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
for (int i = 0; i < GetSize(config.lut_costs); i++)
fprintf(f, "%d %d.00 1.00\n", i+1, config.lut_costs.at(i));
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir).c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, config.show_tempdir));
#ifndef YOSYS_LINK_ABC
abc_output_filter filt(*this, tempdir_name, config.show_tempdir);
@ -1220,7 +1220,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, Ab
temp_stdouterr_r.close();
#endif
if (ret != 0) {
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
return;
}
did_run_abc = true;
@ -1239,7 +1239,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
std::ifstream ifs;
ifs.open(buffer);
if (ifs.fail())
log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
log_error("Can't open ABC output file `%s'.\n", buffer);
bool builtin_lib = config.liberty_files.empty() && config.genlib_files.empty();
RTLIL::Design *mapped_design = new RTLIL::Design;
@ -1490,7 +1490,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
cell_stats.sort();
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
int in_wires = 0, out_wires = 0;
for (auto &si : signal_list)
if (si.is_port) {
@ -1582,7 +1582,7 @@ struct AbcPass : public Pass {
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -1597,41 +1597,41 @@ struct AbcPass : public Pass {
log(" if no -script parameter is given, the following scripts are used:\n");
log("\n");
log(" for -liberty/-genlib without -constr:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB));
log("\n");
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR));
log("\n");
log(" for -lut/-luts (only one LUT size):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}"));
log("\n");
log(" for -lut/-luts (different LUT sizes):\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP));
log("\n");
log(" otherwise:\n");
log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("\n");
log(" for -liberty/-genlib without -constr:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB));
log("\n");
log(" for -liberty/-genlib with -constr:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR));
log("\n");
log(" for -lut/-luts:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT));
log("\n");
log(" for -sop:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP));
log("\n");
log(" otherwise:\n");
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL));
log("\n");
log(" -liberty <file>\n");
log(" generate netlists for the specified cell library (using the liberty\n");

6
passes/techmap/abc9.cc
View file

@ -106,7 +106,7 @@ struct Abc9Pass : public ScriptPass
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -119,12 +119,12 @@ struct Abc9Pass : public ScriptPass
log(" replaced with blanks before the string is passed to ABC.\n");
log("\n");
log(" if no -script parameter is given, the following scripts are used:\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)));
log("\n");
log(" -D <picoseconds>\n");
log(" set delay target. the string {D} in the default scripts above is\n");

14
passes/techmap/abc9_exe.cc
View file

@ -140,7 +140,7 @@ struct abc9_output_filter
return;
}
if (ch == '\n') {
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir));
got_cr = false, linebuf.clear();
return;
}
@ -271,14 +271,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
buffer = stringf("%s/lutdefs.txt", tempdir_name);
f = fopen(buffer.c_str(), "wt");
if (f == NULL)
log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
log_error("Opening %s for writing failed: %s\n", buffer, strerror(errno));
for (int i = 0; i < GetSize(lut_costs); i++)
fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
fclose(f);
}
buffer = stringf("\"%s\" -s -f %s/abc.script 2>&1", exe_file, tempdir_name);
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir));
#ifndef YOSYS_LINK_ABC
abc9_output_filter filt(tempdir_name, show_tempdir);
@ -331,7 +331,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
if (check_file_exists(stringf("%s/output.aig", tempdir_name)))
log_warning("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
else
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer, ret);
}
}
@ -352,7 +352,7 @@ struct Abc9ExePass : public Pass {
#ifdef ABCEXTERNAL
log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
#else
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix().c_str());
log(" use the specified command instead of \"<yosys-bindir>/%syosys-abc\" to execute ABC.\n", proc_program_prefix());
#endif
log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
log("\n");
@ -365,12 +365,12 @@ struct Abc9ExePass : public Pass {
log(" replaced with blanks before the string is passed to ABC.\n");
log("\n");
log(" if no -script parameter is given, the following scripts are used:\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos)));
log("\n");
log(" -fast\n");
log(" use different default scripts that are slightly faster (at the cost\n");
log(" of output quality):\n");
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)).c_str());
log("%s\n", fold_abc9_cmd(RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)));
log("\n");
log(" -constr <file>\n");
log(" pass this file with timing constraints to ABC.\n");

4
passes/techmap/abc9_ops.cc
View file

@ -787,7 +787,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto cell_name : it) {
auto cell = module->cell(cell_name);
log_assert(cell);
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute());
}
}
}
@ -1444,7 +1444,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
}
for (auto &it : cell_stats)
log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
log("ABC RESULTS: %15s cells: %8d\n", it.first, it.second);
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module

4
passes/techmap/attrmap.cc
View file

@ -130,14 +130,14 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
goto delete_this_attr;
if (new_attr != attr)
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname.c_str(),
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second));
new_attributes[new_attr.first] = new_attr.second;
if (0)
delete_this_attr:
log("Removed attribute on %s: %s=%s\n", objname.c_str(), log_id(attr.first), log_const(attr.second));
log("Removed attribute on %s: %s=%s\n", objname, log_id(attr.first), log_const(attr.second));
}
attributes.swap(new_attributes);

4
passes/techmap/clkbufmap.cc
View file

@ -257,14 +257,14 @@ struct ClkbufmapPass : public Pass {
RTLIL::Cell *cell = nullptr;
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", buf_celltype, log_id(module), log_id(wire), i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, log_id(module), log_id(wire), i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);

6
passes/techmap/clockgate.cc
View file

@ -81,7 +81,7 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
} else if (icg_kind == "latch_negedge" || starts_with("latch_negedge_")) {
clk_pol = false;
} else {
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name.c_str(), icg_kind.c_str());
log("Ignoring ICG primitive %s of kind '%s'\n", cell_name, icg_kind);
continue;
}
@ -176,11 +176,11 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
std::optional<ClockGateCell> pos;
std::optional<ClockGateCell> neg;
if (best_pos) {
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name);
pos.emplace(*best_pos);
}
if (best_neg) {
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name);
neg.emplace(*best_neg);
}
return std::make_pair(pos, neg);

6
passes/techmap/dfflegalize.cc
View file

@ -1111,7 +1111,7 @@ struct DffLegalizePass : public Pass {
pol_r = celltype[13];
} else {
unrecognized:
log_error("unrecognized cell type %s.\n", celltype.c_str());
log_error("unrecognized cell type %s.\n", celltype);
}
int mask = 0;
int match = 0;
@ -1140,12 +1140,12 @@ unrecognized:
initmask = 0x555;
} else if (inittype == "r") {
if (srval == 0)
log_error("init type r not valid for cell type %s.\n", celltype.c_str());
log_error("init type r not valid for cell type %s.\n", celltype);
initmask = 0x537;
} else if (inittype == "01") {
initmask = 0x777;
} else {
log_error("unrecognized init type %s for cell type %s.\n", inittype.c_str(), celltype.c_str());
log_error("unrecognized init type %s for cell type %s.\n", inittype, celltype);
}
if (srval == '0') {
initmask &= 0x0ff;

10
passes/techmap/dfflibmap.cc
View file

@ -36,9 +36,9 @@ static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
static void logmap(IdString dff)
{
if (cell_mappings.count(dff) == 0) {
log(" unmapped dff cell: %s\n", dff.c_str());
log(" unmapped dff cell: %s\n", dff);
} else {
log(" %s %s (", cell_mappings[dff].cell_name.c_str(), dff.substr(1).c_str());
log(" %s %s (", cell_mappings[dff].cell_name, dff.substr(1));
bool first = true;
for (auto &port : cell_mappings[dff].ports) {
char arg[3] = { port.second, 0, 0 };
@ -46,7 +46,7 @@ static void logmap(IdString dff)
arg[1] = arg[0] - ('a' - 'A'), arg[0] = '~';
else
arg[1] = arg[0], arg[0] = ' ';
log("%s.%s(%s)", first ? "" : ", ", port.first.c_str(), arg);
log("%s.%s(%s)", first ? "" : ", ", port.first, arg);
first = false;
}
log(");\n");
@ -488,7 +488,7 @@ static void find_cell_sr(std::vector<const LibertyAst *> cells, IdString cell_ty
static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
{
log("Mapping DFF cells in module `%s':\n", module->name.c_str());
log("Mapping DFF cells in module `%s':\n", module->name);
dict<SigBit, pool<Cell*>> notmap;
SigMap sigmap(module);
@ -690,7 +690,7 @@ struct DfflibmapPass : public Pass {
dfflegalize_cmd += stringf(" -cell %s 01", it.first);
dfflegalize_cmd += " t:$_DFF* t:$_SDFF*";
if (info_mode) {
log("dfflegalize command line: %s\n", dfflegalize_cmd.c_str());
log("dfflegalize command line: %s\n", dfflegalize_cmd);
} else {
Pass::call(design, dfflegalize_cmd);
}

16
passes/techmap/extract.cc
View file

@ -627,7 +627,7 @@ struct ExtractPass : public Pass {
for (auto module : map->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(module->name);
log("Creating needle graph %s.\n", graph_name.c_str());
log("Creating needle graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports)) {
solver.addGraph(graph_name, mod_graph);
needle_map[graph_name] = module;
@ -638,7 +638,7 @@ struct ExtractPass : public Pass {
for (auto module : design->modules()) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(module->name);
log("Creating haystack graph %s.\n", graph_name.c_str());
log("Creating haystack graph %s.\n", graph_name);
if (module2graph(mod_graph, module, constports, design, mine_mode ? mine_max_fanout : -1, mine_mode ? &mine_split : nullptr)) {
solver.addGraph(graph_name, mod_graph);
haystack_map[graph_name] = module;
@ -654,7 +654,7 @@ struct ExtractPass : public Pass {
for (auto needle : needle_list)
for (auto &haystack_it : haystack_map) {
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)).c_str(), haystack_it.first.c_str());
log("Solving for %s in %s.\n", ("needle_" + RTLIL::unescape_id(needle->name)), haystack_it.first);
solver.solve(results, "needle_" + RTLIL::unescape_id(needle->name), haystack_it.first, false);
}
log("Found %d matches.\n", GetSize(results));
@ -665,11 +665,11 @@ struct ExtractPass : public Pass {
for (int i = 0; i < int(results.size()); i++) {
auto &result = results[i];
log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId.c_str(), result.haystackGraphId.c_str());
log("\nMatch #%d: (%s in %s)\n", i, result.needleGraphId, result.haystackGraphId);
for (const auto &it : result.mappings) {
log(" %s -> %s", it.first.c_str(), it.second.haystackNodeId.c_str());
log(" %s -> %s", it.first, it.second.haystackNodeId);
for (const auto & it2 : it.second.portMapping)
log(" %s:%s", it2.first.c_str(), it2.second.c_str());
log(" %s:%s", it2.first, it2.second);
log("\n");
}
RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
@ -693,7 +693,7 @@ struct ExtractPass : public Pass {
log("\nFrequent SubCircuit with %d nodes and %d matches:\n", int(result.nodes.size()), result.totalMatchesAfterLimits);
log(" primary match in %s:", log_id(haystack_map.at(result.graphId)->name));
for (auto &node : result.nodes)
log(" %s", RTLIL::unescape_id(node.nodeId).c_str());
log(" %s", RTLIL::unescape_id(node.nodeId));
log("\n");
for (auto &it : result.matchesPerGraph)
log(" matches in %s: %d\n", log_id(haystack_map.at(it.first)->name), it.second);
@ -744,7 +744,7 @@ struct ExtractPass : public Pass {
rewrite_filename(mine_outfile);
f.open(mine_outfile.c_str(), std::ofstream::trunc);
if (f.fail())
log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
log_error("Can't open output file `%s'.\n", mine_outfile);
Backend::backend_call(map, &f, mine_outfile, "rtlil");
f.close();
}

6
passes/techmap/extract_counter.cc
View file

@ -847,7 +847,7 @@ struct ExtractCounterPass : public Pass {
else if (arg == "no")
settings.allow_arst = false;
else
log_error("Invalid -allow_arst value \"%s\"\n", arg.c_str());
log_error("Invalid -allow_arst value \"%s\"\n", arg);
continue;
}
@ -861,7 +861,7 @@ struct ExtractCounterPass : public Pass {
else if (arg == "both")
settings.allowed_dirs = 2;
else
log_error("Invalid -dir value \"%s\"\n", arg.c_str());
log_error("Invalid -dir value \"%s\"\n", arg);
continue;
}
}
@ -893,7 +893,7 @@ struct ExtractCounterPass : public Pass {
for(auto cpair : cells_to_rename)
{
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second.c_str());
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second);
module->rename(cpair.first, cpair.second);
}
}

4
passes/techmap/extract_reduce.cc
View file

@ -133,7 +133,7 @@ struct ExtractReducePass : public Pass
else
continue;
log("Working on cell %s...\n", cell->name.c_str());
log("Working on cell %s...\n", cell->name);
// If looking for a single chain, follow linearly to the sink
pool<Cell*> sinks;
@ -220,7 +220,7 @@ struct ExtractReducePass : public Pass
//We have our list, go act on it
for(auto head_cell : sinks)
{
log(" Head cell is %s\n", head_cell->name.c_str());
log(" Head cell is %s\n", head_cell->name);
//Avoid duplication if we already were covered
if(consumed_cells.count(head_cell))

2
passes/techmap/extractinv.cc
View file

@ -111,7 +111,7 @@ struct ExtractinvPass : public Pass {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, log_id(module), log_id(cell->type), log_id(port.first), i);
sig[i] = SigBit(iwire, i);
}
cell->setPort(port.first, sig);

2
passes/techmap/flowmap.cc
View file

@ -598,7 +598,7 @@ struct FlowmapWorker
continue;
if (!cell->known())
log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
log_error("Cell %s (%s.%s) is unknown.\n", cell->type, log_id(module), log_id(cell));
pool<RTLIL::SigBit> fanout;
for (auto conn : cell->connections())

6
passes/techmap/iopadmap.cc
View file

@ -324,7 +324,7 @@ struct IopadmapPass : public Pass {
if (wire->port_input)
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
@ -348,7 +348,7 @@ struct IopadmapPass : public Pass {
if (!tinoutpad_portname_pad.empty())
rewrite_bits[wire][i] = make_pair(cell, RTLIL::escape_id(tinoutpad_portname_pad));
} else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype);
Cell *cell = module->addCell(
module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
@ -421,7 +421,7 @@ struct IopadmapPass : public Pass {
continue;
}
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype);
if (flag_bits)
{

4
passes/techmap/libcache.cc
View file

@ -117,9 +117,9 @@
if (list) {
log("Caching is %s by default.\n", LibertyAstCache::instance.cache_by_default ? "enabled" : "disabled");
for (auto const &entry : LibertyAstCache::instance.cache_path)
log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first.c_str());
log("Caching is %s for `%s'.\n", entry.second ? "enabled" : "disabled", entry.first);
for (auto const &entry : LibertyAstCache::instance.cached)
log("Data for `%s' is currently cached.\n", entry.first.c_str());
log("Data for `%s' is currently cached.\n", entry.first);
} else if (enable || disable) {
if (all) {
LibertyAstCache::instance.cache_by_default = enable;

6
passes/techmap/libparse.cc
View file

@ -42,7 +42,7 @@ std::shared_ptr<const LibertyAst> LibertyAstCache::cached_ast(const std::string
if (it == cached.end())
return nullptr;
if (verbose)
log("Using cached data for liberty file `%s'\n", fname.c_str());
log("Using cached data for liberty file `%s'\n", fname);
return it->second;
}
@ -53,7 +53,7 @@ void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr
if (!should_cache)
return;
if (verbose)
log("Caching data for liberty file `%s'\n", fname.c_str());
log("Caching data for liberty file `%s'\n", fname);
cached.emplace(fname, ast);
}
@ -671,7 +671,7 @@ void LibertyParser::error(const std::string &str) const
std::stringstream ss;
ss << "Syntax error in liberty file on line " << line << ".\n";
ss << " " << str << "\n";
log_error("%s", ss.str().c_str());
log_error("%s", ss.str());
}
#else

2
passes/techmap/libparse.h
View file

@ -204,7 +204,7 @@ namespace Yosys
}
ast = shared_ast.get();
if (!ast) {
log_error("No entries found in liberty file `%s'.\n", fname.c_str());
log_error("No entries found in liberty file `%s'.\n", fname);
}
}
#endif

10
passes/techmap/techmap.cc
View file

@ -247,7 +247,7 @@ struct TechmapWorker
portname = positional_ports.at(portname);
if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
if (portname.begins_with("$"))
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname, cell->name, tpl->name);
continue;
}
@ -562,7 +562,7 @@ struct TechmapWorker
if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
log("Running \"%s\" on wrapper %s.\n", cmd_string, log_id(extmapper_module));
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
log_continue = true;
@ -580,7 +580,7 @@ struct TechmapWorker
auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
}
@ -589,7 +589,7 @@ struct TechmapWorker
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name, log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
@ -951,7 +951,7 @@ struct TechmapWorker
auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
if (!log_msg_cache.count(msg)) {
log_msg_cache.insert(msg);
log("%s\n", msg.c_str());
log("%s\n", msg);
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
techmap_module_worker(design, module, cell, tpl);