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Remove .c_str() calls from log()/log_error()

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There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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32
passes/sat/eval.cc
View file

@ -87,7 +87,7 @@ struct BruteForceEquivChecker
BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
{
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
log("Checking for equivalence (brute-force): %s vs %s\n", mod1->name, mod2->name);
for (auto w : mod1->wires())
{
if (w->port_id == 0)
@ -264,7 +264,7 @@ struct VlogHammerReporter
if (!ce.eval(sig))
log_error("Can't read back value for port %s!\n", log_id(inputs[i]));
input_pattern_list += stringf(" %s", sig.as_const().as_string());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string().c_str());
log("++PAT++ %d %s %s #\n", idx, log_id(inputs[i]), sig.as_const().as_string());
}
}
@ -280,7 +280,7 @@ struct VlogHammerReporter
ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.size()));
}
log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str());
log("++VAL++ %d %s %s #\n", idx, module_name, sig.as_const().as_string());
if (module_name == "rtl") {
rtl_sig = sig;
@ -294,7 +294,7 @@ struct VlogHammerReporter
sig[i] = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list, sig.as_const().as_string(), module_name);
}
log("++RPT++ ----\n");
@ -307,8 +307,8 @@ struct VlogHammerReporter
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
if (design->module(esc_name) == nullptr)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
log_error("Can't find module %s in current design!\n", name);
log("Using module %s (%s).\n", esc_name, name);
modules.push_back(design->module(esc_name));
module_names.push_back(name);
}
@ -319,15 +319,15 @@ struct VlogHammerReporter
RTLIL::IdString esc_name = RTLIL::escape_id(name);
for (auto mod : modules) {
if (mod->wire(esc_name) == nullptr)
log_error("Can't find input %s in module %s!\n", name.c_str(), log_id(mod->name));
log_error("Can't find input %s in module %s!\n", name, log_id(mod->name));
RTLIL::Wire *port = mod->wire(esc_name);
if (!port->port_input || port->port_output)
log_error("Wire %s in module %s is not an input!\n", name.c_str(), log_id(mod->name));
log_error("Wire %s in module %s is not an input!\n", name, log_id(mod->name));
if (width >= 0 && width != port->width)
log_error("Port %s has different sizes in the different modules!\n", name.c_str());
log_error("Port %s has different sizes in the different modules!\n", name);
width = port->width;
}
log("Using input port %s with width %d.\n", esc_name.c_str(), width);
log("Using input port %s with width %d.\n", esc_name, width);
inputs.push_back(esc_name);
input_widths.push_back(width);
total_input_width += width;
@ -341,9 +341,9 @@ struct VlogHammerReporter
pattern = pattern.substr(1);
}
if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const())
log_error("Failed to parse pattern %s!\n", pattern.c_str());
log_error("Failed to parse pattern %s!\n", pattern);
if (sig.size() < total_input_width)
log_error("Pattern %s is to short!\n", pattern.c_str());
log_error("Pattern %s is to short!\n", pattern);
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits())
@ -352,7 +352,7 @@ struct VlogHammerReporter
else if (bit == RTLIL::State::S1)
bit = RTLIL::State::S0;
}
log("Using pattern %s.\n", patterns.back().as_string().c_str());
log("Using pattern %s.\n", patterns.back().as_string());
}
}
};
@ -415,9 +415,9 @@ struct EvalPass : public Pass {
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
if (design->module(mod1_name) == nullptr)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
log_error("Can't find module `%s'!\n", mod1_name);
if (design->module(mod2_name) == nullptr)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
log_error("Can't find module `%s'!\n", mod2_name);
BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivalent!\n");
@ -574,7 +574,7 @@ struct EvalPass : public Pass {
for (auto &row : tab) {
for (size_t i = 0; i < row.size(); i++) {
int k = int(i) < tab_sep_colidx ? tab_sep_colidx - i - 1 : i;
log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k].c_str());
log(" %s%*s", k == tab_sep_colidx ? "| " : "", tab_column_width[k], row[k]);
}
log("\n");
if (first) {

10
passes/sat/fminit.cc
View file

@ -109,7 +109,7 @@ struct FminitPass : public Pass {
SigSpec clksig;
if (!clocksignal.empty()) {
if (!SigSpec::parse(clksig, module, clocksignal))
log_error("Error parsing expression '%s'.\n", clocksignal.c_str());
log_error("Error parsing expression '%s'.\n", clocksignal);
}
for (auto &it : setdata)
@ -117,10 +117,10 @@ struct FminitPass : public Pass {
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
log_error("Error parsing expression '%s'.\n", it.first);
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second))
log_error("Error parsing expression '%s'.\n", it.second.c_str());
log_error("Error parsing expression '%s'.\n", it.second);
SigSpec final_lhs, final_rhs;
@ -144,7 +144,7 @@ struct FminitPass : public Pass {
SigSpec lhs, rhs;
if (!SigSpec::parse(lhs, module, it.first))
log_error("Error parsing expression '%s'.\n", it.first.c_str());
log_error("Error parsing expression '%s'.\n", it.first);
for (int i = 0; i < GetSize(it.second); i++)
{
@ -183,7 +183,7 @@ struct FminitPass : public Pass {
SigSpec final_lhs, final_rhs;
if (!SigSpec::parse_rhs(lhs, rhs, module, it.second[i]))
log_error("Error parsing expression '%s'.\n", it.second[i].c_str());
log_error("Error parsing expression '%s'.\n", it.second[i]);
for (int i = 0; i < GetSize(rhs); i++)
if (rhs[i] != State::Sz) {

4
passes/sat/freduce.cc
View file

@ -247,7 +247,7 @@ struct PerformReduction
string loop_signals;
for (auto loop_bit : recursion_guard)
loop_signals += string(" ") + log_signal(loop_bit);
log_error("Found logic loop:%s\n", loop_signals.c_str());
log_error("Found logic loop:%s\n", loop_signals);
}
recursion_guard.insert(out);
@ -596,7 +596,7 @@ struct FreduceWorker
void dump()
{
std::string filename = stringf("%s_%s_%05d.il", dump_prefix, RTLIL::id2cstr(module->name), reduce_counter);
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename.c_str());
log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename);
Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : ""));
}

8
passes/sat/mutate.cc
View file

@ -539,7 +539,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
std::ofstream sout;
sout.open(srcsfile, std::ios::out | std::ios::trunc);
if (!sout.is_open())
log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str());
log_error("Could not open file \"%s\" with write access.\n", srcsfile);
sources.sort();
for (auto &s : sources)
sout << s << std::endl;
@ -550,7 +550,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
if (!filename.empty()) {
fout.open(filename, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
log_error("Could not open file \"%s\" with write access.\n", filename);
}
int ctrl_value = opts.ctrl_value;
@ -561,7 +561,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
str += " -mode none";
if (filename.empty())
log("%s\n", str.c_str());
log("%s\n", str);
else
fout << str << std::endl;
}
@ -588,7 +588,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
for (auto &s : entry.src)
str += stringf(" -src %s", s);
if (filename.empty())
log("%s\n", str.c_str());
log("%s\n", str);
else
fout << str << std::endl;
}

22
passes/sat/qbfsat.cc
View file

@ -122,7 +122,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
for (auto &it : hole_assignments) {
RTLIL::SigSpec lhs(it.first);
RTLIL::SigSpec rhs(it.second);
log("Specializing %s from file with %s = %d.\n", module->name.c_str(), log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0);
log("Specializing %s from file with %s = %d.\n", module->name, log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0);
module->connect(lhs, rhs);
}
}
@ -151,7 +151,7 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet =
RTLIL::SigSpec lhs(hole_sigbit.wire, hole_sigbit.offset, 1);
RTLIL::State hole_bit_val = hole_value[bit_idx] == '1'? RTLIL::State::S1 : RTLIL::State::S0;
if (!quiet)
log("Specializing %s with %s = %d.\n", module->name.c_str(), log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1)
log("Specializing %s with %s = %d.\n", module->name, log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1)
;
module->connect(lhs, hole_bit_val);
}
@ -168,7 +168,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wi
allconst->setPort(ID::Y, input);
allconst->set_src_attribute(input->get_src_attribute());
input->port_input = false;
log("Replaced input %s with $allconst cell.\n", n.c_str());
log("Replaced input %s with $allconst cell.\n", n);
}
module->fixup_ports();
}
@ -184,7 +184,7 @@ void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
else {
log("Adding $assume cell for output(s): ");
for (auto w : wires_to_assume)
log("\"%s\" ", w->name.c_str());
log("\"%s\" ", w->name);
log("\n");
}
@ -236,10 +236,10 @@ QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt,
log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
else
if (opt.show_smtbmc && !quiet)
log("smtbmc output: %s", line.c_str());
log("smtbmc output: %s", line);
};
log_header(mod->design, "Solving QBF-SAT problem.\n");
if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd.c_str());
if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd);
int64_t begin = PerformanceTimer::query();
run_command(smtbmc_cmd, process_line);
int64_t end = PerformanceTimer::query();
@ -303,7 +303,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
log_assert(wire_to_optimize_name != "");
log_assert(module->wire(wire_to_optimize_name) != nullptr);
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name.c_str());
log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name);
//If maximizing, grow until we get a failure. Then bisect success and failure.
while (failure == 0 || difference(success, failure) > 1) {
@ -316,7 +316,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
: module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1));
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), cur_thresh);
log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh);
}
ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num);
@ -337,7 +337,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
log_assert(value.is_fully_const());
success = value.as_const().as_int();
best_soln = ret;
log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name.c_str(), success);
log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name, success);
Pass::call(design, "design -pop");
module = design->module(module_name);
@ -355,7 +355,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
break;
}
else
log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), failure);
log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), failure);
}
iter_num++;
@ -367,7 +367,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
cur_thresh = (success + failure) / 2; //bisection
}
if (success != 0 || failure != 0) {
log("Wire %s is %s at %d.\n", wire_to_optimize_name.c_str(), (maximize? "maximized" : "minimized"), success);
log("Wire %s is %s at %d.\n", wire_to_optimize_name, (maximize? "maximized" : "minimized"), success);
ret = best_soln;
}
}

12
passes/sat/sat.cc
View file

@ -652,9 +652,9 @@ struct SatHelper
log(" ");
if (info.width <= 32 && !found_undef)
log("%-*s %11d %9x %*s\n", maxModelName+5, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+3, value.as_string().c_str());
log("%-*s %11d %9x %*s\n", maxModelName+5, info.description, value.as_int(), value.as_int(), maxModelWidth+3, value.as_string());
else
log("%-*s %11s %9s %*s\n", maxModelName+5, info.description.c_str(), "--", "--", maxModelWidth+3, value.as_string().c_str());
log("%-*s %11s %9s %*s\n", maxModelName+5, info.description, "--", "--", maxModelWidth+3, value.as_string());
}
if (last_timestep == -2)
@ -668,7 +668,7 @@ struct SatHelper
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno));
log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str());
log("Dumping SAT model to VCD file %s\n", vcd_file_name);
time_t timestamp;
struct tm* now;
@ -772,7 +772,7 @@ struct SatHelper
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno));
log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name.c_str());
log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name);
int mintime = 1, maxtime = 0, maxwidth = 0;;
dict<string, pair<int, dict<int, Const>>> wavedata;
@ -1530,7 +1530,7 @@ struct SatPass : public Pass {
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();
inductstep.ez->printDIMACS(f, false);
@ -1634,7 +1634,7 @@ struct SatPass : public Pass {
if (!f)
log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
log("Dumping CNF to file `%s'.\n", cnf_file_name);
cnf_file_name.clear();
sathelper.ez->printDIMACS(f, false);

60
passes/sat/sim.cc
View file

@ -60,10 +60,10 @@ static double stringToTime(std::string str)
long value = strtol(str.c_str(), &endptr, 10);
if (g_units.find(endptr)==g_units.end())
log_error("Cannot parse '%s', bad unit '%s'\n", str.c_str(), endptr);
log_error("Cannot parse '%s', bad unit '%s'\n", str, endptr);
if (value < 0)
log_error("Time value '%s' must be positive\n", str.c_str());
log_error("Time value '%s' must be positive\n", str);
return value * pow(10.0, g_units.at(endptr));
}
@ -430,7 +430,7 @@ struct SimInstance
value.bits().push_back(State::Sz);
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value));
return value;
}
@ -449,7 +449,7 @@ struct SimInstance
}
if (shared->debug)
log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value));
return did_something;
}
@ -551,7 +551,7 @@ struct SimInstance
if (has_y) sig_y = cell->getPort(ID::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type));
// Simple (A -> Y) and (A,B -> Y) cells
if (has_a && !has_c && !has_d && !has_s && has_y) {
@ -793,14 +793,14 @@ struct SimInstance
static void log_source(RTLIL::AttrObject *src)
{
for (auto src : src->get_strpool_attribute(ID::src))
log(" %s\n", src.c_str());
log(" %s\n", src);
}
void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell)
{
log_assert(cell->module == module);
bool has_src = cell->has_attribute(ID::src);
log("%s %s%s\n", opening_verbiage.c_str(),
log("%s %s%s\n", opening_verbiage,
log_id(cell), has_src ? " at" : "");
log_source(cell);
@ -894,7 +894,7 @@ struct SimInstance
}
std::string rendered = print.fmt.render();
log("%s", rendered.c_str());
log("%s", rendered);
shared->display_output.emplace_back(shared->step, this, cell, rendered);
}
}
@ -921,15 +921,15 @@ struct SimInstance
}
if (cell->type == ID($cover) && en == State::S1 && a == State::S1)
log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
log("Cover %s.%s (%s) reached.\n", hiername(), log_id(cell), label);
if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
log("Assumption %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
if (cell->type == ID($assert) && en == State::S1 && a != State::S1) {
log_cell_w_hierarchy("Failed assertion", cell);
if (shared->serious_asserts)
log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
log_error("Assertion %s.%s (%s) failed.\n", hiername(), log_id(cell), label);
else
log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
}
@ -952,7 +952,7 @@ struct SimInstance
{
if (!ff_database.empty() || !mem_database.empty()) {
if (wbmods.count(module))
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername(), log_id(module));
wbmods.insert(module);
}
@ -1192,7 +1192,7 @@ struct SimInstance
}
}
if (!found)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(sig_y.as_wire()->name)));
}
}
}
@ -1478,7 +1478,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
}
for (auto portname : clockn)
@ -1490,7 +1490,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
}
@ -1500,7 +1500,7 @@ struct SimWorker : SimShared
if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
top->fst_inputs[wire] = id;
}
}
@ -1623,9 +1623,9 @@ struct SimWorker : SimShared
else if (type == "latch")
mem_latches[variable] = { memid, offset };
else
log_error("Map file addressing cell %s as type %s\n", symbol.c_str(), type.c_str());
log_error("Map file addressing cell %s as type %s\n", symbol, type);
} else {
log_error("Cell %s in map file is not memory cell\n", symbol.c_str());
log_error("Cell %s in map file is not memory cell\n", symbol);
}
} else {
if (index < w->start_offset || index > w->start_offset + w->width)
@ -1645,7 +1645,7 @@ struct SimWorker : SimShared
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
log_error("Can not open file `%s`\n", sim_filename.c_str());
log_error("Can not open file `%s`\n", sim_filename);
int state = 0;
std::string status;
@ -1729,7 +1729,7 @@ struct SimWorker : SimShared
if (pos==std::string::npos) {
pos = name.find_first_of("#");
if (pos==std::string::npos)
log_error("Line does not contain proper signal name `%s`\n", name.c_str());
log_error("Line does not contain proper signal name `%s`\n", name);
}
return name.substr(0, pos);
}
@ -1744,7 +1744,7 @@ struct SimWorker : SimShared
std::ifstream f;
f.open(sim_filename.c_str());
if (f.fail() || GetSize(sim_filename) == 0)
log_error("Can not open file `%s`\n", sim_filename.c_str());
log_error("Can not open file `%s`\n", sim_filename);
int state = 0;
int cycle = 0;
@ -1874,7 +1874,7 @@ struct SimWorker : SimShared
if (item.wire != nullptr) {
if (paths.count(path)) {
if (debug)
log("witness hierarchy: found wire %s\n", path.str().c_str());
log("witness hierarchy: found wire %s\n", path.str());
bool inserted = hierarchy.paths.emplace(path, {instance, item.wire, {}, INT_MIN}).second;
if (!inserted)
log_warning("Yosys witness path `%s` is ambiguous in this design\n", path.str().c_str());
@ -1883,7 +1883,7 @@ struct SimWorker : SimShared
auto it = mem_paths.find(path);
if (it != mem_paths.end()) {
if (debug)
log("witness hierarchy: found mem %s\n", path.str().c_str());
log("witness hierarchy: found mem %s\n", path.str());
IdPath word_path = path;
word_path.emplace_back();
for (auto addr_part : it->second) {
@ -1951,7 +1951,7 @@ struct SimWorker : SimShared
Const value = yw.get_bits(t, signal.bits_offset, signal.width);
if (debug)
log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value));
log("yw: set %s to %s\n", signal.path.str(), log_const(value));
if (found_path.wire != nullptr) {
found_path.instance->set_state_parent_drivers(
@ -2052,7 +2052,7 @@ struct SimWorker : SimShared
PrettyJson json;
if (!json.write_to_file(summary_filename))
log_error("Can't open file `%s' for writing: %s\n", summary_filename.c_str(), strerror(errno));
log_error("Can't open file `%s' for writing: %s\n", summary_filename, strerror(errno));
json.begin_object();
json.entry("version", "Yosys sim summary");
@ -2134,7 +2134,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2147,7 +2147,7 @@ struct SimWorker : SimShared
log_error("Clock port %s on module %s is not input.\n", log_id(portname), log_id(top->module));
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(portname));
if (id==0)
log_error("Can't find port %s.%s in FST.\n", scope.c_str(), log_id(portname));
log_error("Can't find port %s.%s in FST.\n", scope, log_id(portname));
fst_clock.push_back(id);
clocks[w] = id;
}
@ -2159,7 +2159,7 @@ struct SimWorker : SimShared
for (auto wire : topmod->wires()) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0 && (wire->port_input || wire->port_output))
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)));
if (wire->port_input)
if (clocks.find(wire)==clocks.end())
inputs[wire] = id;
@ -2236,7 +2236,7 @@ struct SimWorker : SimShared
f << "\n";
f << "\tinteger i;\n";
uint64_t prev_time = startCount;
log("Writing data to `%s`\n", (tb_filename+".txt").c_str());
log("Writing data to `%s`\n", (tb_filename+".txt"));
std::ofstream data_file(tb_filename+".txt");
std::stringstream initstate;
unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX;
@ -2292,7 +2292,7 @@ struct SimWorker : SimShared
f << "\tend\n";
f << "endmodule\n";
log("Writing testbench to `%s`\n", (tb_filename+".v").c_str());
log("Writing testbench to `%s`\n", (tb_filename+".v"));
std::ofstream tb_file(tb_filename+".v");
tb_file << f.str();

2
passes/sat/synthprop.cc
View file

@ -170,7 +170,7 @@ void SynthPropWorker::run()
std::ofstream fout;
fout.open(map_file, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", map_file.c_str());
log_error("Could not open file \"%s\" with write access.\n", map_file);
for (auto name : tracing_data[module].names) {
fout << name << std::endl;