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Remove .c_str() calls from log()/log_error()

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There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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4
passes/proc/proc_arst.cc
View file

@ -204,7 +204,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
bool polarity = sync->type == RTLIL::SyncType::STp;
if (check_signal(mod, root_sig, sync->signal, polarity)) {
if (edge_syncs.size() > 1) {
log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name);
sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0;
arst_syncs.push_back(sync);
edge_syncs.erase(it);
@ -223,7 +223,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
sync->mem_write_actions.clear();
eliminate_const(mod, &proc->root_case, root_sig, polarity);
} else {
log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name);
eliminate_const(mod, &proc->root_case, root_sig, !polarity);
}
did_something = true;

4
passes/proc/proc_clean.cc
View file

@ -171,7 +171,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool
proc_clean_case(&proc->root_case, did_something, count, -1);
}
if (count > 0 && !quiet)
log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str());
log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name, proc->name);
total_count += count;
}
@ -215,7 +215,7 @@ struct ProcCleanPass : public Pass {
if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
proc->root_case.actions.size() == 0) {
if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name);
delme.push_back(proc);
}
}

6
passes/proc/proc_dff.cc
View file

@ -106,7 +106,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
cell->setPort(ID::CLK, clk);
cell->setPort(ID::ALOAD, set);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name,
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
}
@ -136,9 +136,9 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
cell->setPort(ID::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative");
else
log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
log(" created %s cell `%s' with global clock", cell->type, cell->name);
if (arst)
log(" and %s level reset", arst_polarity ? "positive" : "negative");
log(".\n");

2
passes/proc/proc_dlatch.cc
View file

@ -404,7 +404,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
for (auto &bit : lhs) {
State val = db.initvals(bit);
if (db.initvals(bit) != State::Sx) {
log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str());
log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name, log_signal(bit), db.module->name, proc->name);
}
db.initvals.remove_init(bit);
}

2
passes/proc/proc_init.cc
View file

@ -31,7 +31,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
for (auto &sync : proc->syncs)
if (sync->type == RTLIL::SyncType::STi)
{
log("Found init rule in `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
log("Found init rule in `%s.%s'.\n", mod->name, proc->name);
for (auto &action : sync->actions)
{

2
passes/proc/proc_mux.cc
View file

@ -412,7 +412,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
{
log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
log("Creating decoders for process `%s.%s'.\n", mod->name, proc->name);
SigSnippets sigsnip;
sigsnip.insert(&proc->root_case);