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Remove .c_str() calls from log()/log_error()

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There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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12
passes/hierarchy/hierarchy.cc
View file

@ -59,7 +59,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
std::set<RTLIL::IdString> portnames;
std::set<RTLIL::IdString> parameters;
std::map<RTLIL::IdString, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
log("Generate module for cell type %s:\n", celltype);
for (auto mod : design->modules())
for (auto cell : mod->cells())
@ -605,9 +605,9 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
return;
if (indent == 0)
log("Top module: %s\n", mod->name.c_str());
log("Top module: %s\n", mod->name);
else if (!mod->get_blackbox_attribute())
log("Used module: %*s%s\n", indent, "", mod->name.c_str());
log("Used module: %*s%s\n", indent, "", mod->name);
used.insert(mod);
for (auto cell : mod->cells()) {
@ -647,7 +647,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
for (auto mod : del_modules) {
if (!purge_lib && mod->get_blackbox_attribute())
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
log("Removing unused module `%s'.\n", mod->name);
design->remove(mod);
del_counter++;
}
@ -873,11 +873,11 @@ struct HierarchyPass : public Pass {
log("Port declaration: %s", decl.input ? decl.output ? "inout" : "input" : "output");
if (decl.index >= 1)
log(" [at position %d]", decl.index);
log(" %s\n", decl.portname.c_str());
log(" %s\n", decl.portname);
generate_ports.push_back(decl);
continue;
is_celltype:
log("Celltype: %s\n", args[argidx].c_str());
log("Celltype: %s\n", args[argidx]);
generate_cells.push_back(RTLIL::unescape_id(args[argidx]));
}
continue;

16
passes/hierarchy/submod.cc
View file

@ -87,7 +87,7 @@ struct SubmodWorker
void handle_submodule(SubModule &submod)
{
log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name);
wire_flags.clear();
for (RTLIL::Cell *cell : submod.cells) {
@ -192,13 +192,13 @@ struct SubmodWorker
}
if (new_wire->port_input && new_wire->port_output)
log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: inout %s\n", wire->name, new_wire->name);
else if (new_wire->port_input)
log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: input %s\n", wire->name, new_wire->name);
else if (new_wire->port_output)
log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str());
log(" signal %s: output %s\n", wire->name, new_wire->name);
else
log(" signal %s: internal\n", wire->name.c_str());
log(" signal %s: internal\n", wire->name);
flags.new_wire = new_wire;
}
@ -214,7 +214,7 @@ struct SubmodWorker
log_assert(wire_flags.count(bit.wire) > 0);
bit.wire = wire_flags.at(bit.wire).new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
log(" cell %s (%s)\n", new_cell->name, new_cell->type);
if (!copy_mode)
module->remove(cell);
}
@ -250,12 +250,12 @@ struct SubmodWorker
return;
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}
if (module->memories.size() > 0) {
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name);
return;
}