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https://github.com/YosysHQ/yosys
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Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
parent
c2291c10a6
commit
e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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@ -140,7 +140,7 @@ struct FsmExpand
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{
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optimze_as_needed();
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log(" merging %s cell %s.\n", cell->type.c_str(), cell->name.c_str());
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log(" merging %s cell %s.\n", cell->type, cell->name);
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merged_set.insert(cell);
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already_optimized = false;
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@ -243,7 +243,7 @@ struct FsmExpand
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void execute()
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{
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log("\n");
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log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
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log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name);
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already_optimized = false;
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limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
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@ -76,7 +76,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
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kiss_file.open(kiss_name, std::ios::out | std::ios::trunc);
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if (!kiss_file.is_open()) {
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log_error("Could not open file \"%s\" with write access.\n", kiss_name.c_str());
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log_error("Could not open file \"%s\" with write access.\n", kiss_name);
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}
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fsm_data.copy_from_cell(cell);
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@ -71,7 +71,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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{
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
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log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
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log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name);
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return false;
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}
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@ -255,7 +255,7 @@ undef_bit_in_next_state:
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static void extract_fsm(RTLIL::Wire *wire)
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{
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log("Extracting FSM `%s' from module `%s'.\n", wire->name.c_str(), module->name.c_str());
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log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name);
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// get input and output signals for state ff
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@ -274,7 +274,7 @@ static void extract_fsm(RTLIL::Wire *wire)
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
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continue;
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log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
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log(" found %s cell for state register: %s\n", cell->type, cell->name);
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RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
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RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
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clk = cell->getPort(ID::CLK);
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@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
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static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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{
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log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name.c_str(), module->name.c_str());
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log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name, module->name);
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FsmData fsm_data;
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fsm_data.copy_from_cell(fsm_cell);
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@ -293,7 +293,7 @@ struct FsmOpt
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FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module)
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{
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log("Optimizing FSM `%s' from module `%s'.\n", cell->name.c_str(), module->name.c_str());
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log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name);
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fsm_data.copy_from_cell(cell);
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this->cell = cell;
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@ -56,15 +56,15 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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{
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std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto";
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log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
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log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding);
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if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
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log(" unknown encoding `%s': using auto instead.\n", encoding.c_str());
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log(" unknown encoding `%s': using auto instead.\n", encoding);
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encoding = "auto";
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}
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if (encoding == "none" || encoding == "user") {
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log(" nothing to do for encoding `%s'.\n", encoding.c_str());
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log(" nothing to do for encoding `%s'.\n", encoding);
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return;
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}
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@ -79,7 +79,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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encoding = default_encoding;
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else
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encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary";
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log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str());
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log(" mapping auto encoding to `%s` for this FSM.\n", encoding);
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}
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if (encoding == "one-hot") {
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@ -93,7 +93,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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}
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fsm_data.state_bits = new_num_state_bits;
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} else
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log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
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log_error("FSM encoding `%s' is not supported!\n", encoding);
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if (encfile)
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fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
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@ -113,7 +113,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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} else
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log_abort();
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log(" %s -> %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
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log(" %s -> %s\n", fsm_data.state_table[i].as_string(), new_code.as_string());
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if (encfile)
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fprintf(encfile, ".map %s %s\n", fsm_data.state_table[i].as_string().c_str(), new_code.as_string().c_str());
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fsm_data.state_table[i] = new_code;
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@ -165,13 +165,13 @@ struct FsmRecodePass : public Pass {
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if (arg == "-fm_set_fsm_file" && argidx+1 < args.size() && fm_set_fsm_file == NULL) {
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fm_set_fsm_file = fopen(args[++argidx].c_str(), "w");
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if (fm_set_fsm_file == NULL)
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log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
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log_error("Can't open fm_set_fsm_file `%s' for writing: %s\n", args[argidx], strerror(errno));
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continue;
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}
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if (arg == "-encfile" && argidx+1 < args.size() && encfile == NULL) {
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encfile = fopen(args[++argidx].c_str(), "w");
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if (encfile == NULL)
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log_error("Can't open encfile `%s' for writing: %s\n", args[argidx].c_str(), strerror(errno));
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log_error("Can't open encfile `%s' for writing: %s\n", args[argidx], strerror(errno));
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continue;
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}
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if (arg == "-encoding" && argidx+1 < args.size() && default_encoding.empty()) {
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@ -134,7 +134,7 @@ struct FsmData
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{
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log("-------------------------------------\n");
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log("\n");
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log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
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log(" Information on FSM %s (%s):\n", cell->name, cell->parameters[ID::NAME].decode_string());
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log("\n");
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log(" Number of input signals: %3d\n", num_inputs);
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log(" Number of output signals: %3d\n", num_outputs);
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