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Remove .c_str() calls from log()/log_error()

Browse source 
There are some leftovers, but this is an easy regex-based approach that removes most of them.
This commit is contained in:
Robert O'Callahan 2025-09-11 05:25:26 +00:00
parent c2291c10a6
commit e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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2
passes/cmds/abstract.cc
View file

@ -67,7 +67,7 @@ struct Slice {
int wire_offset(RTLIL::Wire *wire, int index) const {
int rtl_offset = indices == RtlilSlice ? index : wire->from_hdl_index(index);
if (rtl_offset < 0 || rtl_offset >= wire->width) {
log_error("Slice %s is out of bounds for wire %s in module %s", to_string().c_str(), log_id(wire), log_id(wire->module));
log_error("Slice %s is out of bounds for wire %s in module %s", to_string(), log_id(wire), log_id(wire->module));
}
return rtl_offset;
}

14
passes/cmds/add.cc
View file

@ -38,22 +38,22 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_assert(is_formal_celltype(celltype));
if (wire == nullptr) {
log_error("Could not find wire with name \"%s\".\n", name.c_str());
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
RTLIL::Wire *enable_wire = module->wire(escaped_enable_name);
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}
}
@ -79,7 +79,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (wire == nullptr)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name);
}
else
{
@ -91,7 +91,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
if (!flag_global)
@ -110,7 +110,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
cell->setPort(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str());
log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type);
}
}

2
passes/cmds/cover.cc
View file

@ -146,7 +146,7 @@ struct CoverPass : public Pass {
for (auto f : out_files)
fprintf(f, "%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
if (do_log)
log("%-60s %10d %s\n", it.second.first.c_str(), it.second.second, it.first.c_str());
log("%-60s %10d %s\n", it.second.first, it.second.second, it.first);
}
#else
for (auto f : out_files)

2
passes/cmds/edgetypes.cc
View file

@ -105,7 +105,7 @@ struct EdgetypePass : public Pass {
edge_cache.sort();
for (auto &str : edge_cache)
log("%s\n", str.c_str());
log("%s\n", str);
}
} EdgetypePass;

2
passes/cmds/exec.cc
View file

@ -172,7 +172,7 @@ struct ExecPass : public Pass {
std::string line = linebuf.substr(0, pos);
linebuf.erase(0, pos + 1);
if (!flag_quiet)
log("%s\n", line.c_str());
log("%s\n", line);
if (flag_expect_stdout)
for(auto &x : expect_stdout)

2
passes/cmds/glift.cc
View file

@ -343,7 +343,7 @@ private:
//with taint signals and connect the new ports to the corresponding taint signals.
RTLIL::Module *cell_module_def = module->design->module(cell->type);
dict<RTLIL::IdString, RTLIL::SigSpec> orig_ports = cell->connections();
log("Adding cell %s\n", cell_module_def->name.c_str());
log("Adding cell %s\n", cell_module_def->name);
for (auto &it : orig_ports) {
RTLIL::SigSpec port = it.second;
RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port);

8
passes/cmds/internal_stats.cc
View file

@ -100,15 +100,15 @@ struct InternalStatsPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
if (auto mem = current_mem_bytes()) {
log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str());
log(" \"memory_now\": %s,\n", std::to_string(*mem));
}
auto ast_bytes = AST::astnode_count() * (unsigned long long) sizeof(AST::AstNode);
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes).c_str());
log(" \"memory_ast\": %s,\n", std::to_string(ast_bytes));
}
// stats go here

4
passes/cmds/linecoverage.cc
View file

@ -85,7 +85,7 @@ struct CoveragePass : public Pass {
if (!ofile.empty()) {
fout.open(ofile, std::ios::out | std::ios::trunc);
if (!fout.is_open())
log_error("Could not open file \"%s\" with write access.\n", ofile.c_str());
log_error("Could not open file \"%s\" with write access.\n", ofile);
}
std::map<std::string, std::set<int>> uncovered_lines;
@ -128,7 +128,7 @@ struct CoveragePass : public Pass {
for (const auto& file_entry : all_lines) {
int lines_found = file_entry.second.size();
int lines_hit = file_entry.second.size() - (uncovered_lines.count(file_entry.first) ? uncovered_lines[file_entry.first].size() : 0);
log("File %s: %d/%d lines covered\n", file_entry.first.c_str(), lines_hit, lines_found);
log("File %s: %d/%d lines covered\n", file_entry.first, lines_hit, lines_found);
if(!ofile.empty()) {
fout << "SF:" << file_entry.first << "\n";

2
passes/cmds/logcmd.cc
View file

@ -106,7 +106,7 @@ struct LogPass : public Pass {
if (to_stdout) fprintf(stdout, "%s%s", text.c_str(), line_end);
if (to_stderr) fprintf(stderr, "%s%s", text.c_str(), line_end);
if (to_log) {
if (!header) log("%s%s", text.c_str(), line_end);
if (!header) log("%s%s", text, line_end);
else log_header(design, "%s%s", text.c_str(), line_end);
}
}

8
passes/cmds/logger.cc
View file

@ -108,7 +108,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to warn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to warn list.\n", pattern);
log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -120,7 +120,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to nowarn list.\n", pattern.c_str());
log("Added regex '%s' for warnings to nowarn list.\n", pattern);
log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -132,7 +132,7 @@ struct LoggerPass : public Pass {
std::string pattern = args[++argidx];
if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2);
try {
log("Added regex '%s' for warnings to werror list.\n", pattern.c_str());
log("Added regex '%s' for warnings to werror list.\n", pattern);
log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern));
}
catch (const std::regex_error& e) {
@ -152,7 +152,7 @@ struct LoggerPass : public Pass {
}
if (args[argidx] == "-experimental" && argidx+1 < args.size()) {
std::string value = args[++argidx];
log("Added '%s' experimental ignore list.\n", value.c_str());
log("Added '%s' experimental ignore list.\n", value);
log_experimentals_ignored.insert(value);
continue;
}

6
passes/cmds/plugin.cc
View file

@ -187,11 +187,11 @@ struct PluginPass : public Pass {
log("Loaded plugins:\n");
for (auto &it : loaded_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#ifdef WITH_PYTHON
for (auto &it : loaded_python_plugins)
log(" %s\n", it.first.c_str());
log(" %s\n", it.first);
#endif
if (!loaded_plugin_aliases.empty()) {
@ -200,7 +200,7 @@ struct PluginPass : public Pass {
for (auto &it : loaded_plugin_aliases)
max_alias_len = max(max_alias_len, GetSize(it.first));
for (auto &it : loaded_plugin_aliases)
log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
log("Alias: %-*s %s\n", max_alias_len, it.first, it.second);
}
}
}

2
passes/cmds/portarcs.cc
View file

@ -278,7 +278,7 @@ struct PortarcsPass : Pass {
log("\n");
for (auto bit : outputs) {
log(" %10s ", bit_str(bit).c_str());
log(" %10s ", bit_str(bit));
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++)
log("\033[48;5;%dm ", 232 + ((std::max(p[i], 0) * 24) - 1) / max_delay);

2
passes/cmds/portlist.cc
View file

@ -75,7 +75,7 @@ struct PortlistPass : public Pass {
}
log("module %s%s\n", log_id(module), m_mode ? " (" : "");
for (int i = 0; i < GetSize(ports); i++)
log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
log("%s%s\n", ports[i], m_mode && i+1 < GetSize(ports) ? "," : "");
if (m_mode)
log(");\nendmodule\n");
};

10
passes/cmds/printattrs.cc
View file

@ -47,9 +47,9 @@ struct PrintAttrsPass : public Pass {
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags & RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
log("%s(* %s=%s *)\n", get_indent_str(indent), log_id(s), x.as_string());
else
log_assert(x.flags & RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
}
@ -63,14 +63,14 @@ struct PrintAttrsPass : public Pass {
for (auto mod : design->selected_modules())
{
if (design->selected_whole_module(mod)) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name));
log("%s%s\n", get_indent_str(indent), log_id(mod->name));
indent += 2;
for (auto &it : mod->attributes)
log_const(it.first, it.second, indent);
}
for (auto cell : mod->selected_cells()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name));
log("%s%s\n", get_indent_str(indent), log_id(cell->name));
indent += 2;
for (auto &it : cell->attributes)
log_const(it.first, it.second, indent);
@ -78,7 +78,7 @@ struct PrintAttrsPass : public Pass {
}
for (auto wire : mod->selected_wires()) {
log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name));
log("%s%s\n", get_indent_str(indent), log_id(wire->name));
indent += 2;
for (auto &it : wire->attributes)
log_const(it.first, it.second, indent);

6
passes/cmds/rename.cc
View file

@ -577,7 +577,7 @@ struct RenamePass : public Pass {
new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_wire_names[wire].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename wire %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename wire %s -> %s\n", name, new_name);
}
for (auto cell : module->selected_cells()) {
@ -590,7 +590,7 @@ struct RenamePass : public Pass {
new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name));
auto new_name = new_cell_names[cell].str().substr(1);
if (VERILOG_BACKEND::id_is_verilog_escaped(new_name))
log_error("Failed to rename cell %s -> %s\n", name.c_str(), new_name.c_str());
log_error("Failed to rename cell %s -> %s\n", name, new_name);
}
for (auto &it : new_wire_names)
@ -629,7 +629,7 @@ struct RenamePass : public Pass {
if (module_to_rename != nullptr) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", module_to_rename->name.c_str(), to_name.c_str());
log("Renaming module %s to %s.\n", module_to_rename->name, to_name);
design->rename(module_to_rename, to_name);
} else
log_cmd_error("Object `%s' not found!\n", from_name.c_str());

2
passes/cmds/scc.cc
View file

@ -101,7 +101,7 @@ struct SccWorker
design(design), module(module), sigmap(module)
{
if (module->processes.size() > 0) {
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name);
return;
}

18
passes/cmds/scratchpad.cc
View file

@ -76,18 +76,18 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-get" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier)) {
log("%s\n", design->scratchpad_get_string(identifier).c_str());
log("%s\n", design->scratchpad_get_string(identifier));
} else if (RTLIL::constpad.count(identifier)) {
log("%s\n", RTLIL::constpad.at(identifier).c_str());
log("%s\n", RTLIL::constpad.at(identifier));
} else {
log("\"%s\" not set\n", identifier.c_str());
log("\"%s\" not set\n", identifier);
}
continue;
}
if (args[argidx] == "-set" && argidx+2 < args.size()) {
string identifier = args[++argidx];
if (RTLIL::constpad.count(identifier))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier);
string value = args[++argidx];
if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2);
design->scratchpad_set_string(identifier, value);
@ -107,9 +107,9 @@ struct ScratchpadPass : public Pass {
else if (RTLIL::constpad.count(identifier_from))
value = RTLIL::constpad.at(identifier_from);
else
log_error("\"%s\" not set\n", identifier_from.c_str());
log_error("\"%s\" not set\n", identifier_from);
if (RTLIL::constpad.count(identifier_to))
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to.c_str());
log_error("scratchpad entry \"%s\" is a global constant\n", identifier_to);
design->scratchpad_set_string(identifier_to, value);
continue;
}
@ -118,7 +118,7 @@ struct ScratchpadPass : public Pass {
string expected = args[++argidx];
if (expected.front() == '\"' && expected.back() == '\"') expected = expected.substr(1, expected.size() - 2);
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
string value = design->scratchpad_get_string(identifier);
if (value != expected) {
log_error("scratchpad entry '%s' is set to '%s' instead of the asserted '%s'\n",
@ -129,13 +129,13 @@ struct ScratchpadPass : public Pass {
if (args[argidx] == "-assert-set" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) == 0)
log_error("scratchpad entry '%s' is not defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is not defined\n", identifier);
continue;
}
if (args[argidx] == "-assert-unset" && argidx+1 < args.size()) {
string identifier = args[++argidx];
if (design->scratchpad.count(identifier) > 0)
log_error("scratchpad entry '%s' is defined\n", identifier.c_str());
log_error("scratchpad entry '%s' is defined\n", identifier);
continue;
}
break;

16
passes/cmds/select.cc
View file

@ -632,20 +632,20 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
if (rule.cell_types.size() > 0) {
log(" cell types:");
for (auto &it : rule.cell_types)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
if (rule.port_names.size() > 0) {
log(" port names:");
for (auto &it : rule.port_names)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
}
if (limits.size() > 0) {
log(" limits:");
for (auto &it : limits)
log(" %s", it.c_str());
log(" %s", it);
log("\n");
}
#endif
@ -1443,7 +1443,7 @@ struct SelectPass : public Pass {
std::ifstream f(read_file);
yosys_input_files.insert(read_file);
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
log_error("Can't open '%s' for reading: %s\n", read_file, strerror(errno));
auto sel = RTLIL::Selection::EmptySelection(design);
string line;
@ -1518,7 +1518,7 @@ struct SelectPass : public Pass {
f = fopen(write_file.c_str(), "w");
yosys_output_files.insert(write_file);
if (f == nullptr)
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
log_error("Can't open '%s' for writing: %s\n", write_file, strerror(errno));
}
if (work_stack.size() > 0)
design->push_selection(work_stack.back());
@ -1573,7 +1573,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is not empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1588,7 +1588,7 @@ struct SelectPass : public Pass {
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
std::string desc = describe_selection_for_assert(design, sel, true);
log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str());
log_error("Assertion failed: selection is empty:%s\n%s", sel_str, desc);
}
return;
}
@ -1645,7 +1645,7 @@ struct SelectPass : public Pass {
if (!unset_name.empty())
{
if (!design->selection_vars.erase(unset_name))
log_error("Selection '%s' does not exist!\n", unset_name.c_str());
log_error("Selection '%s' does not exist!\n", unset_name);
return;
}

6
passes/cmds/setundef.cc
View file

@ -41,7 +41,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
if (module->count_id(name) != 0)
{
log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
log("Module %s already has such an object %s.\n", module->name, name);
name += "$";
return add_wire(module, name, width, flag_input, flag_output);
}
@ -56,7 +56,7 @@ static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width
module->fixup_ports();
}
log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
log("Added wire %s to module %s.\n", name, module->name);
}
return wire;
@ -319,7 +319,7 @@ struct SetundefPass : public Pass {
wire = add_wire(module, name, c.width, true, false);
module->connect(RTLIL::SigSig(c, wire));
}
log("Exposing undriven wire %s as input.\n", wire->name.c_str());
log("Exposing undriven wire %s as input.\n", wire->name);
}
module->fixup_ports();
}

12
passes/cmds/show.cc
View file

@ -188,7 +188,7 @@ struct ShowWorker
if (enumerateIds) {
if (autonames.count(id) == 0) {
autonames[id] = autonames.size() + 1;
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id.c_str());
log("Generated short name for internal identifier: _%d_ -> %s\n", autonames[id], id);
}
id = stringf("_%d_", autonames[id]);
} else if (abbreviateIds) {
@ -895,7 +895,7 @@ struct ShowPass : public Pass {
f.open(filename.c_str());
yosys_input_files.insert(filename);
if (f.fail())
log_error("Can't open lib file `%s'.\n", filename.c_str());
log_error("Can't open lib file `%s'.\n", filename);
RTLIL::Design *lib = new RTLIL::Design;
Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog"));
libs.push_back(lib);
@ -907,7 +907,7 @@ struct ShowPass : public Pass {
std::string dot_file = stringf("%s.dot", prefix);
std::string out_file = stringf("%s.%s", prefix, format.empty() ? "svg" : format);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = fopen(dot_file.c_str(), "w");
if (custom_prefix)
yosys_output_files.insert(dot_file);
@ -934,7 +934,7 @@ struct ShowPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -954,7 +954,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -964,7 +964,7 @@ struct ShowPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

2
passes/cmds/splice.cc
View file

@ -345,7 +345,7 @@ struct SplicePass : public Pass {
for (auto module : design->selected_modules())
{
if (module->processes.size()) {
log("Skipping module %s as it contains processes.\n", module->name.c_str());
log("Skipping module %s as it contains processes.\n", module->name);
continue;
}

74
passes/cmds/stat.cc
View file

@ -285,7 +285,7 @@ struct statdata_t {
cell_area.at(cell_type).is_sequential = cell_data.is_sequential;
}
} else {
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type.c_str(),
log_error("double_parameter_area for %s has %d parameters, but only 2 are expected.\n", cell_type,
(int)cell_data.double_parameter_area.size());
}
}
@ -452,22 +452,22 @@ struct statdata_t {
if (print_area) {
if (print_hierarchical) {
log(" %s %s %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), count_local_str.c_str(),
log(" %s %s %s %s %s%s\n", count_global_str, area_global_str, count_local_str,
area_local_str.c_str(), indent.c_str(), name.c_str());
} else if (print_global_only) {
log(" %s %s %s%s\n", count_global_str.c_str(), area_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, area_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s %s%s\n", count_local_str.c_str(), area_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_local_str, area_local_str, indent, name);
}
} else {
if (print_hierarchical) {
log(" %s %s %s%s\n", count_global_str.c_str(), count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s %s%s\n", count_global_str, count_local_str, indent, name);
} else if (print_global_only) {
log(" %s %s%s\n", count_global_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_global_str, indent, name);
} else {
if (count_local > 0)
log(" %s %s%s\n", count_local_str.c_str(), indent.c_str(), name.c_str());
log(" %s %s%s\n", count_local_str, indent, name);
}
}
}
@ -540,13 +540,13 @@ struct statdata_t {
if (!unknown_cell_area.empty()) {
log("\n");
for (auto cell_type : unknown_cell_area)
log(" Area for cell type %s is unknown!\n", cell_type.c_str());
log(" Area for cell type %s is unknown!\n", cell_type);
}
if (area != 0) {
log("\n");
if (print_hierarchical || print_global_only) {
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, area);
log(" of which used for sequential elements: %f (%.2f%%)\n", sequential_area, 100.0 * sequential_area / area);
} else {
double local_area = 0;
@ -555,7 +555,7 @@ struct statdata_t {
double local_sequential_area = 0;
for (auto &it : local_seq_area_cells_by_type)
local_sequential_area += it.second;
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), local_area);
log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name, local_area);
log(" of which used for sequential elements: %f (%.2f%%)\n", local_sequential_area,
100.0 * local_sequential_area / local_area);
}
@ -587,19 +587,19 @@ struct statdata_t {
if (!first_module)
log(",\n");
if (hierarchical) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0).c_str());
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0).c_str());
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0).c_str());
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0).c_str());
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0).c_str());
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0).c_str());
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0).c_str());
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0).c_str());
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0).c_str());
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area).c_str());
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area).c_str());
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area).c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %s,\n", json_line(local_num_wires, 0, num_wires, 0));
log(" \"num_wire_bits\": %s,\n", json_line(local_num_wire_bits, 0, num_wire_bits, 0));
log(" \"num_pub_wires\": %s,\n", json_line(local_num_pub_wires, 0, num_pub_wires, 0));
log(" \"num_pub_wire_bits\": %s,\n", json_line(local_num_pub_wire_bits, 0, num_pub_wire_bits, 0));
log(" \"num_ports\": %s,\n", json_line(local_num_ports, 0, num_ports, 0));
log(" \"num_port_bits\": %s,\n", json_line(local_num_port_bits, 0, num_port_bits, 0));
log(" \"num_memories\": %s,\n", json_line(local_num_memories, 0, num_memories, 0));
log(" \"num_memory_bits\": %s,\n", json_line(local_num_memory_bits, 0, num_memory_bits, 0));
log(" \"num_processes\": %s,\n", json_line(local_num_processes, 0, num_processes, 0));
log(" \"num_cells\": %s,\n", json_line(local_num_cells, local_area, num_cells, area));
log(" \"num_submodules\": %s,\n", json_line(0, 0, num_submodules, submodule_area));
log(" \"sequential_area\": %s,\n", json_line(0, local_sequential_area, 0, sequential_area));
log(" \"num_cells_by_type\": {\n");
bool first_line = true;
@ -607,7 +607,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(local_num_cells_by_type.count(it.first) ? local_num_cells_by_type.at(it.first) : 0,
local_area_cells_by_type.count(it.first) ? local_area_cells_by_type.at(it.first) : 0, it.second,
area_cells_by_type.at(it.first))
@ -621,7 +621,7 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %s", json11::Json(log_id(it.first)).dump().c_str(),
log(" %s: %s", json11::Json(log_id(it.first)).dump(),
json_line(0, 0, it.second,
submodules_area_by_type.count(it.first) ? submodules_area_by_type.at(it.first) : 0)
.c_str());
@ -640,7 +640,7 @@ struct statdata_t {
} else {
if (global_only) {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", num_wires);
log(" \"num_wire_bits\": %u,\n", num_wire_bits);
log(" \"num_pub_wires\": %u,\n", num_pub_wires);
@ -662,20 +662,20 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
log(" }");
} else {
log(" %s: {\n", json11::Json(mod_name).dump().c_str());
log(" %s: {\n", json11::Json(mod_name).dump());
log(" \"num_wires\": %u,\n", local_num_wires);
log(" \"num_wire_bits\": %u,\n", local_num_wire_bits);
log(" \"num_pub_wires\": %u,\n", local_num_pub_wires);
@ -697,14 +697,14 @@ struct statdata_t {
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
for (auto &it : num_submodules_by_type)
if (it.second) {
if (!first_line)
log(",\n");
log(" %s: %u", json11::Json(log_id(it.first)).dump().c_str(), it.second);
log(" %s: %u", json11::Json(log_id(it.first)).dump(), it.second);
first_line = false;
}
log("\n");
@ -824,11 +824,11 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
double value = std::stod(s);
single_parameter_area.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse single parameter area value '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse single parameter area value '%s': %s\n", s, e.what());
}
}
if (single_parameter_area.size() == 0)
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1].c_str());
log_error("single parameter area has size 0: %s\n", sar->args[single_parameter_area.size() - 1]);
// check if it is a double parameterised area
}
const LibertyAst *dar = cell->find("double_area_parameterised");
@ -857,12 +857,12 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
value = std::stod(s);
cast_sub_array.push_back(value);
} catch (const std::exception &e) {
log_error("Failed to parse double parameter area value for '%s': %s\n", s.c_str(), e.what());
log_error("Failed to parse double parameter area value for '%s': %s\n", s, e.what());
}
}
double_parameter_area.push_back(cast_sub_array);
if (cast_sub_array.size() == 0)
log_error("double paramter array has size 0: %s\n", s.c_str());
log_error("double paramter array has size 0: %s\n", s);
}
}
const LibertyAst *par = cell->find("port_names");
@ -973,10 +973,10 @@ struct StatPass : public Pass {
if (json_mode) {
log("{\n");
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump().c_str());
log(" \"creator\": %s,\n", json11::Json(yosys_maybe_version()).dump());
std::stringstream invocation;
std::copy(args.begin(), args.end(), std::ostream_iterator<std::string>(invocation, " "));
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump());
log(" \"modules\": {\n");
}

4
passes/cmds/timeest.cc
View file

@ -322,7 +322,7 @@ struct EstimateSta {
std::string src_attr = cell->get_src_attribute();
cell_src = stringf(" source: %s", src_attr);
}
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src.c_str());
log(" cell %s (%s)%s\n", log_id(cell), log_id(cell->type), cell_src);
printed.insert(cell);
}
} else {
@ -333,7 +333,7 @@ struct EstimateSta {
std::string src_attr = bit.wire->get_src_attribute();
wire_src = stringf(" source: %s", src_attr);
}
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src.c_str(), levels[node]);
log(" wire %s%s (level %ld)\n", log_signal(bit), wire_src, levels[node]);
}
}

8
passes/cmds/viz.cc
View file

@ -988,7 +988,7 @@ struct VizPass : public Pass {
if (custom_prefix)
yosys_output_files.insert(dot_file);
log("Writing dot description to `%s'.\n", dot_file.c_str());
log("Writing dot description to `%s'.\n", dot_file);
FILE *f = nullptr;
auto open_dot_file = [&]() {
if (f != nullptr) return;
@ -1028,7 +1028,7 @@ struct VizPass : public Pass {
#endif
std::string cmd = stringf(DOT_CMD, format, dot_file, out_file, out_file, out_file);
#undef DOT_CMD
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
#if !defined(YOSYS_DISABLE_SPAWN)
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
@ -1047,7 +1047,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("%s '%s' %s", viewer_exe, out_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
} else
@ -1057,7 +1057,7 @@ struct VizPass : public Pass {
#else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file, dot_file, dot_file, dot_file, background);
#endif
log("Exec: %s\n", cmd.c_str());
log("Exec: %s\n", cmd);
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
}

4
passes/cmds/wrapcell.cc
View file

@ -59,7 +59,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
auto beg = it;
while (it != fmt.end() && *it != '}') it++;
if (it == fmt.end()) {
log("Unclosed curly brackets in format string '%s'\n", fmt.c_str());
log("Unclosed curly brackets in format string '%s'\n", fmt);
return {};
}
@ -70,7 +70,7 @@ std::optional<std::string> format_with_params(std::string fmt, const dict<IdStri
} else {
auto id = RTLIL::escape_id(std::string(beg, it));
if (!parameters.count(id)) {
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt);
return {};
}