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Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
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parent
c2291c10a6
commit
e0ae7b7af4
140 changed files with 623 additions and 623 deletions
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@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
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std::string id = RTLIL::escape_id(std::string(expr, id_len));
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if (!module->wires_.count(id))
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log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
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log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id));
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expr += id_len;
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return module->wires_.at(id);
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@ -550,7 +550,7 @@ struct LibertyFrontend : public Frontend {
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name));
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std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
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parse_type_map(type_map, cell);
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@ -582,9 +582,9 @@ struct LibertyFrontend : public Frontend {
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{
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if (!flag_ignore_miss_dir)
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{
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log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
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log_error("Missing or invalid direction for pin %s on cell %s.\n", node->args.at(0), log_id(module->name));
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} else {
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log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
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log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0));
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delete module;
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goto skip_cell;
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}
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@ -596,7 +596,7 @@ struct LibertyFrontend : public Frontend {
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if (node->id == "bus" && node->args.size() == 1)
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{
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if (flag_ignore_buses) {
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log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str());
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log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0));
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delete module;
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goto skip_cell;
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}
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@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend {
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}
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if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))
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log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
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log_error("Missing or invalid direction for bus %s on cell %s.\n", node->args.at(0), log_id(module->name));
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simple_comb_cell = false;
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