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Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak

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Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
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Emil J 2025-07-10 19:56:56 +02:00 • committed by GitHub
commit dfe86b50d8
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2 changed files with 6 additions and 10 deletions
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12
kernel/log.cc
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@ -664,15 +664,9 @@ const char *log_const(const RTLIL::Const &value, bool autoint)
const char *log_id(const RTLIL::IdString &str) const char *log_id(const RTLIL::IdString &str)
{ {
log_id_cache.push_back(strdup(str.c_str())); std::string unescaped = RTLIL::unescape_id(str);
const char *p = log_id_cache.back(); log_id_cache.push_back(strdup(unescaped.c_str()));
if (p[0] != '\\') return log_id_cache.back();
return p;
if (p[1] == '$' || p[1] == '\\' || p[1] == 0)
return p;
if (p[1] >= '0' && p[1] <= '9')
return p;
return p+1;
} }
const char *log_str(const char *str) const char *log_str(const char *str)

4
kernel/satgen.h
View file

@ -101,7 +101,9 @@ struct SatGen
else else
vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
} else { } else {
std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset)); std::string wire_name = RTLIL::unescape_id(bit.wire->name);
std::string name = pf +
(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset));
vec.push_back(ez->frozen_literal(name)); vec.push_back(ez->frozen_literal(name));
imported_signals[pf][bit] = vec.back(); imported_signals[pf][bit] = vec.back();
} }