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	sdc: add -keep_hierarchy test
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							|  | @ -890,6 +890,7 @@ MK_TEST_DIRS += tests/arch/xilinx | |||
| MK_TEST_DIRS += tests/bugpoint | ||||
| MK_TEST_DIRS += tests/opt | ||||
| MK_TEST_DIRS += tests/sat | ||||
| MK_TEST_DIRS += tests/sdc | ||||
| MK_TEST_DIRS += tests/sim | ||||
| MK_TEST_DIRS += tests/svtypes | ||||
| MK_TEST_DIRS += tests/techmap | ||||
|  |  | |||
							
								
								
									
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								tests/sdc/alu_sub.sdc
									
										
									
									
									
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								tests/sdc/alu_sub.sdc
									
										
									
									
									
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							|  | @ -0,0 +1,70 @@ | |||
| ############################################################################### | ||||
| # Created by write_sdc | ||||
| # Fri Oct  3 11:26:00 2025 | ||||
| ############################################################################### | ||||
| current_design wrapper | ||||
| ############################################################################### | ||||
| # Timing Constraints | ||||
| ############################################################################### | ||||
| create_clock -name this_clk -period 1.0000 [get_ports {clk}] | ||||
| create_clock -name that_clk -period 2.0000  | ||||
| create_clock -name another_clk -period 2.0000 \ | ||||
|     [list [get_ports {A[0]}]\ | ||||
|           [get_ports {A[1]}]\ | ||||
|           [get_ports {A[2]}]\ | ||||
|           [get_ports {A[3]}]\ | ||||
|           [get_ports {A[4]}]\ | ||||
|           [get_ports {A[5]}]\ | ||||
|           [get_ports {A[6]}]\ | ||||
|           [get_ports {A[7]}]\ | ||||
|           [get_ports {B[0]}]\ | ||||
|           [get_ports {B[1]}]\ | ||||
|           [get_ports {B[2]}]\ | ||||
|           [get_ports {B[3]}]\ | ||||
|           [get_ports {B[4]}]\ | ||||
|           [get_ports {B[5]}]\ | ||||
|           [get_ports {B[6]}]\ | ||||
|           [get_ports {B[7]}]] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[0]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[0]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[1]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[1]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[2]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[2]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[3]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[3]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[4]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[4]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[5]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[5]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[6]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[6]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[7]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[7]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[0]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[0]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[1]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[1]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[2]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[2]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[3]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[3]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[4]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[4]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[5]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[5]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[6]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[6]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[7]}] | ||||
| set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[7]}] | ||||
| group_path -name operation_group\ | ||||
|     -through [list [get_nets {alu/operation[0]}]\ | ||||
|            [get_nets {alu/operation[1]}]\ | ||||
|            [get_nets {alu/operation[2]}]\ | ||||
|            [get_nets {alu/operation[3]}]] | ||||
| ############################################################################### | ||||
| # Environment | ||||
| ############################################################################### | ||||
| ############################################################################### | ||||
| # Design Rules | ||||
| ############################################################################### | ||||
							
								
								
									
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								tests/sdc/alu_sub.v
									
										
									
									
									
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								tests/sdc/alu_sub.v
									
										
									
									
									
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							|  | @ -0,0 +1,62 @@ | |||
| module adder( | ||||
|     input [7:0] a, input [7:0] b, output [7:0] y | ||||
| ); | ||||
|     assign y = a + b; | ||||
| endmodule | ||||
| 
 | ||||
| module wrapper( | ||||
| 	input clk, | ||||
| 	input [7:0] A, | ||||
| 	input [7:0] B, | ||||
| 	input [3:0] op, | ||||
| 	output reg [7:0] result | ||||
| ); | ||||
| 	wire CF, ZF, SF; | ||||
| 	alu alu( | ||||
| 		.clk(clk), | ||||
| 		.A(A), | ||||
| 		.B(B), | ||||
| 		.operation(op), | ||||
| 		.result(result), | ||||
| 		.CF(CF), | ||||
| 		.ZF(ZF), | ||||
| 		.SF(SF) | ||||
| 	); | ||||
| endmodule | ||||
| 
 | ||||
| module alu( | ||||
| 	input clk, | ||||
| 	input [7:0] A, | ||||
| 	input [7:0] B, | ||||
| 	input [3:0] operation, | ||||
| 	output reg [7:0] result, | ||||
| 	output reg CF, | ||||
| 	output reg ZF, | ||||
| 	output reg SF | ||||
| ); | ||||
| 
 | ||||
| 	localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000; | ||||
| 	localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001; | ||||
| 
 | ||||
| 	reg [8:0] tmp; | ||||
| 	reg [7:0] added; | ||||
| 
 | ||||
| 	adder adder(.a(A), .b(B), .y(added)); | ||||
| 
 | ||||
| 	always @(posedge clk) | ||||
| 	begin | ||||
| 		case (operation) | ||||
| 			ALU_OP_ADD : | ||||
| 				tmp = added; | ||||
| 			ALU_OP_SUB : | ||||
| 				tmp = A - B; | ||||
| 		endcase | ||||
| 
 | ||||
| 		CF <= tmp[8]; | ||||
| 		ZF <= tmp[7:0] == 0; | ||||
| 		SF <= tmp[7]; | ||||
| 
 | ||||
| 		result <= tmp[7:0]; | ||||
| 	end | ||||
| endmodule | ||||
| 
 | ||||
							
								
								
									
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								tests/sdc/alu_sub.ys
									
										
									
									
									
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							|  | @ -0,0 +1,14 @@ | |||
| read_verilog alu_sub.v | ||||
| proc | ||||
| hierarchy -auto-top | ||||
| 
 | ||||
| select -assert-mod-count 1 adder | ||||
| select -assert-mod-count 1 wrapper | ||||
| select -assert-mod-count 1 alu | ||||
| 
 | ||||
| sdc -keep_hierarchy alu_sub.sdc | ||||
| flatten | ||||
| 
 | ||||
| select -assert-mod-count 0 adder | ||||
| select -assert-mod-count 1 wrapper | ||||
| select -assert-mod-count 1 alu | ||||
							
								
								
									
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								tests/sdc/run-test.sh
									
										
									
									
									
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							|  | @ -0,0 +1,4 @@ | |||
| #!/usr/bin/env bash | ||||
| set -eu | ||||
| source ../gen-tests-makefile.sh | ||||
| generate_mk --yosys-scripts --bash | ||||
							
								
								
									
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								tests/sdc/side-effects.sdc
									
										
									
									
									
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							|  | @ -0,0 +1,2 @@ | |||
| puts "This should print something:" | ||||
| puts [get_ports {A[0]}] | ||||
							
								
								
									
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							|  | @ -0,0 +1,4 @@ | |||
| #!/usr/bin/env bash | ||||
| 
 | ||||
| ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something: | ||||
| YOSYS_SDC_MAGIC_NODE_0' | ||||
|  | @ -1,5 +0,0 @@ | |||
| puts "SDC constraints file says hello from arbitrary Tcl execution" | ||||
| set_false_path -from [get_pins s1/sa] -to [get_pins s1/sb] | ||||
| puts "This should print something:" | ||||
| puts [get_ports a b] | ||||
| puts "Did it?" | ||||
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