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https://github.com/YosysHQ/yosys
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sdc: add -keep_hierarchy test
This commit is contained in:
Emil J. Tywoniak
parent
e341bbb80d
commit
dead2aa03f
8 changed files with 157 additions and 5 deletions
1
Makefile
1
Makefile
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@ -890,6 +890,7 @@ MK_TEST_DIRS += tests/arch/xilinx
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MK_TEST_DIRS += tests/bugpoint
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MK_TEST_DIRS += tests/opt
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MK_TEST_DIRS += tests/sat
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MK_TEST_DIRS += tests/sdc
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MK_TEST_DIRS += tests/sim
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MK_TEST_DIRS += tests/svtypes
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MK_TEST_DIRS += tests/techmap
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70
tests/sdc/alu_sub.sdc
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70
tests/sdc/alu_sub.sdc
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@ -0,0 +1,70 @@
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###############################################################################
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# Created by write_sdc
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# Fri Oct 3 11:26:00 2025
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###############################################################################
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current_design wrapper
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name this_clk -period 1.0000 [get_ports {clk}]
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create_clock -name that_clk -period 2.0000
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create_clock -name another_clk -period 2.0000 \
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[list [get_ports {A[0]}]\
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[get_ports {A[1]}]\
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[get_ports {A[2]}]\
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[get_ports {A[3]}]\
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[get_ports {A[4]}]\
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[get_ports {A[5]}]\
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[get_ports {A[6]}]\
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[get_ports {A[7]}]\
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[get_ports {B[0]}]\
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[get_ports {B[1]}]\
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[get_ports {B[2]}]\
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[get_ports {B[3]}]\
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[get_ports {B[4]}]\
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[get_ports {B[5]}]\
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[get_ports {B[6]}]\
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[get_ports {B[7]}]]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[0]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[0]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[1]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[1]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[2]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[2]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[3]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[3]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[4]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[4]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[5]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[5]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[6]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[6]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {A[7]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {A[7]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[0]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[0]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[1]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[1]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[2]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[2]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[3]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[3]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[4]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[4]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[5]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[5]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[6]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[6]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -rise -min -add_delay [get_ports {B[7]}]
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set_input_delay 1.0000 -clock [get_clocks {this_clk}] -fall -min -add_delay [get_ports {B[7]}]
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group_path -name operation_group\
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-through [list [get_nets {alu/operation[0]}]\
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[get_nets {alu/operation[1]}]\
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[get_nets {alu/operation[2]}]\
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[get_nets {alu/operation[3]}]]
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###############################################################################
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# Environment
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###############################################################################
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###############################################################################
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# Design Rules
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###############################################################################
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62
tests/sdc/alu_sub.v
Normal file
62
tests/sdc/alu_sub.v
Normal file
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@ -0,0 +1,62 @@
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module adder(
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input [7:0] a, input [7:0] b, output [7:0] y
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);
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assign y = a + b;
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endmodule
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module wrapper(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] op,
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output reg [7:0] result
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);
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wire CF, ZF, SF;
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alu alu(
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.clk(clk),
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.A(A),
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.B(B),
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.operation(op),
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.result(result),
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.CF(CF),
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.ZF(ZF),
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.SF(SF)
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);
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endmodule
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module alu(
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input clk,
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input [7:0] A,
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input [7:0] B,
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input [3:0] operation,
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output reg [7:0] result,
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output reg CF,
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output reg ZF,
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output reg SF
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);
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localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000;
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localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001;
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reg [8:0] tmp;
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reg [7:0] added;
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adder adder(.a(A), .b(B), .y(added));
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always @(posedge clk)
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begin
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case (operation)
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ALU_OP_ADD :
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tmp = added;
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ALU_OP_SUB :
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tmp = A - B;
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endcase
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CF <= tmp[8];
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ZF <= tmp[7:0] == 0;
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SF <= tmp[7];
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result <= tmp[7:0];
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end
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endmodule
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14
tests/sdc/alu_sub.ys
Normal file
14
tests/sdc/alu_sub.ys
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@ -0,0 +1,14 @@
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read_verilog alu_sub.v
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proc
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hierarchy -auto-top
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select -assert-mod-count 1 adder
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select -assert-mod-count 1 wrapper
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select -assert-mod-count 1 alu
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sdc -keep_hierarchy alu_sub.sdc
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flatten
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select -assert-mod-count 0 adder
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select -assert-mod-count 1 wrapper
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select -assert-mod-count 1 alu
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4
tests/sdc/run-test.sh
Executable file
4
tests/sdc/run-test.sh
Executable file
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@ -0,0 +1,4 @@
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#!/usr/bin/env bash
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set -eu
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source ../gen-tests-makefile.sh
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generate_mk --yosys-scripts --bash
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2
tests/sdc/side-effects.sdc
Normal file
2
tests/sdc/side-effects.sdc
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@ -0,0 +1,2 @@
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puts "This should print something:"
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puts [get_ports {A[0]}]
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4
tests/sdc/side-effects.sh
Executable file
4
tests/sdc/side-effects.sh
Executable file
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@ -0,0 +1,4 @@
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#!/usr/bin/env bash
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../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something:
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YOSYS_SDC_MAGIC_NODE_0'
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@ -1,5 +0,0 @@
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puts "SDC constraints file says hello from arbitrary Tcl execution"
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set_false_path -from [get_pins s1/sa] -to [get_pins s1/sb]
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puts "This should print something:"
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puts [get_ports a b]
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puts "Did it?"
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