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fix input -> output timings

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This commit is contained in:
Artur Swiderski 2020-12-06 14:07:41 +01:00
parent 8e893dbf23
commit dd9c11c035
2 changed files with 27 additions and 27 deletions
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37
techlibs/intel_le/common/le_sim.v
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@ -25,7 +25,7 @@
// Cyclone V LUT output timings (picoseconds): // Cyclone V LUT output timings (picoseconds):
// //
// CARRY A B C D // CARRY A B C D
// COMBOUT ?408? 319 323 211 114 // COMBOUT ?408? 332 337 220 119
// CARRYOUT 200 376 385 ? - // CARRYOUT 200 376 385 ? -
@ -36,10 +36,10 @@ parameter [15:0] LUT = 16'h0000;
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => Q) = 319; (A => Q) = 337;
(B => Q) = 323; (B => Q) = 332;
(C => Q) = 211; (C => Q) = 220;
(D => Q) = 114; (D => Q) = 119;
endspecify endspecify
`endif `endif
@ -55,9 +55,9 @@ parameter [7:0] LUT = 8'h00;
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => Q) = 510; (A => Q) = 332;
(B => Q) = 400; (B => Q) = 220;
(C => Q) = 97; (C => Q) = 119;
endspecify endspecify
`endif `endif
assign Q = LUT >> {C, B, A}; assign Q = LUT >> {C, B, A};
@ -72,8 +72,8 @@ parameter [3:0] LUT = 4'h0;
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => Q) = 400; (A => Q) = 220;
(B => Q) = 97; (B => Q) = 119;
endspecify endspecify
`endif `endif
assign Q = LUT >> {B, A}; assign Q = LUT >> {B, A};
@ -86,7 +86,7 @@ module MISTRAL_NOT(input A, output Q);
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => Q) = 97; (A => Q) = 119;
endspecify endspecify
`endif `endif
assign Q = ~A; assign Q = ~A;
@ -98,16 +98,17 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO
parameter LUT = 16'h0000; parameter LUT = 16'h0000;
`ifdef cycloneiv `ifdef cycloneiv
specify specify
(A => SO) = 1342; (A => SO) = 337;
(B => SO) = 1323; (B => SO) = 332;
(C => SO) = 927; (C => SO) = 220;
(D => SO) = 887; (D => SO) = 119;
(CI => SO) = 368; (CI => SO) = 08;
(A => CO) = 376; (A => CO) = 385;
(B => CO) = 385; (B => CO) = 376;
(CI => CO) = 200; (CI => CO) = 200;
endspecify endspecify
`endif `endif

11
tests/arch/intel_le/mux.ys
View file

@ -17,9 +17,8 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3 select -assert-count 3 t:MISTRAL_ALUT3
select -assert-count 2 t:MISTRAL_ALUT4 select -assert-none t:MISTRAL_ALUT3 %% t:* %D
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
@ -29,7 +28,7 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 2 t:MISTRAL_ALUT2 select -assert-count 3 t:MISTRAL_ALUT2
select -assert-count 5 t:MISTRAL_ALUT4 select -assert-count 5 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
@ -40,7 +39,7 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-max 4 t:MISTRAL_ALUT3 select -assert-max 3 t:MISTRAL_ALUT3
select -assert-max 9 t:MISTRAL_ALUT4 select -assert-max 10 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D