diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v
index eeaafaa32..50a25cb4b 100644
--- a/techlibs/intel_le/common/le_sim.v
+++ b/techlibs/intel_le/common/le_sim.v
@@ -25,7 +25,7 @@
 // Cyclone V LUT output timings (picoseconds):
 //
 //          CARRY   A    B    C   D  
-//  COMBOUT  ?408? 319  323  211 114  
+//  COMBOUT  ?408? 332  337  220 119  
 // CARRYOUT   200  376  385    ?   -
 
 
@@ -36,10 +36,10 @@ parameter [15:0] LUT = 16'h0000;
 
 `ifdef cycloneiv
 specify
-    (A => Q) = 319;
-    (B => Q) = 323;
-    (C => Q) = 211;
-    (D => Q) = 114;
+    (A => Q) = 337; 
+    (B => Q) = 332;
+    (C => Q) = 220;
+    (D => Q) = 119;
 endspecify
 `endif
 
@@ -55,9 +55,9 @@ parameter [7:0] LUT = 8'h00;
 
 `ifdef cycloneiv 
 specify 
-    (A => Q) = 510;
-    (B => Q) = 400;
-    (C => Q) = 97;
+    (A => Q) = 332;
+    (B => Q) = 220;
+    (C => Q) = 119;
 endspecify
 `endif
 assign Q = LUT >> {C, B, A};
@@ -72,8 +72,8 @@ parameter [3:0] LUT = 4'h0;
 
 `ifdef cycloneiv 
 specify
-    (A => Q) = 400;
-    (B => Q) = 97;
+    (A => Q) = 220;
+    (B => Q) = 119;
 endspecify
 `endif
 assign Q = LUT >> {B, A};
@@ -84,9 +84,9 @@ endmodule
 (* abc9_lut=1, lib_whitebox *)
 module MISTRAL_NOT(input A, output Q);
 
-`ifdef cycloneiv 
+`ifdef cycloneiv  
 specify
-    (A => Q) = 97;
+    (A => Q) = 119;
 endspecify
 `endif
 assign Q = ~A;
@@ -98,16 +98,17 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO
 
 parameter LUT = 16'h0000;
 
-`ifdef cycloneiv  
-specify
-    (A  => SO) = 1342;
-    (B  => SO) = 1323;
-    (C  => SO) = 927;
-    (D => SO) = 887;
-    (CI => SO) = 368;
 
-    (A  => CO) = 376;
-    (B  => CO) = 385;
+`ifdef cycloneiv   
+specify
+    (A  => SO) = 337;
+    (B  => SO) = 332;
+    (C  => SO) = 220;
+    (D => SO) = 119;
+    (CI => SO) = 08;
+
+    (A  => CO) = 385;
+    (B  => CO) = 376;
     (CI => CO) = 200;
 endspecify
 `endif
diff --git a/tests/arch/intel_le/mux.ys b/tests/arch/intel_le/mux.ys
index 7c4a4bb33..169cef00c 100644
--- a/tests/arch/intel_le/mux.ys
+++ b/tests/arch/intel_le/mux.ys
@@ -17,9 +17,8 @@ proc
 equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-count 2 t:MISTRAL_ALUT4
-select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
+select -assert-count 3 t:MISTRAL_ALUT3
+select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 
 
 
@@ -29,7 +28,7 @@ proc
 equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 2 t:MISTRAL_ALUT2
+select -assert-count 3 t:MISTRAL_ALUT2
 select -assert-count 5 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
 
@@ -40,7 +39,7 @@ proc
 equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-max 4 t:MISTRAL_ALUT3
-select -assert-max 9 t:MISTRAL_ALUT4
+select -assert-max 3 t:MISTRAL_ALUT3
+select -assert-max 10 t:MISTRAL_ALUT4
 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D