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fix input -> output timings

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This commit is contained in:
Artur Swiderski 2020-12-06 14:07:41 +01:00
parent 8e893dbf23
commit dd9c11c035
2 changed files with 27 additions and 27 deletions
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11
tests/arch/intel_le/mux.ys
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@ -17,9 +17,8 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-count 2 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
@ -29,7 +28,7 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 2 t:MISTRAL_ALUT2
select -assert-count 3 t:MISTRAL_ALUT2
select -assert-count 5 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D
@ -40,7 +39,7 @@ proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 4 t:MISTRAL_ALUT3
select -assert-max 9 t:MISTRAL_ALUT4
select -assert-max 3 t:MISTRAL_ALUT3
select -assert-max 10 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D