mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-19 09:40:21 +00:00
Code Activity

Detect and reject cases that do not map well to iCE40 DSPs (yet)

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-20 11:18:19 +01:00
parent 62493c91b2
commit dca65d83a0
2 changed files with 17 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

10
passes/pmgen/ice40_dsp.pmg
View file

@ -100,6 +100,16 @@ code addAB sigS
addAB = addB;
sigS = port(addB, \A);
}
if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB);
int actual_mul_width = GetSize(sigY);
int actual_acc_width = GetSize(sigS);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
reject;
}
endcode
match muxA