mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-29 15:37:59 +00:00
Add examples/osu035
This commit is contained in:
parent
664ba4d80e
commit
dca3b3cd5f
4 changed files with 30 additions and 0 deletions
3
examples/osu035/example.v
Normal file
3
examples/osu035/example.v
Normal file
|
@ -0,0 +1,3 @@
|
|||
module top (input clk, input [7:0] a, b, output reg [15:0] c);
|
||||
always @(posedge clk) c <= a * b;
|
||||
endmodule
|
Loading…
Add table
Add a link
Reference in a new issue