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Add examples/osu035

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Clifford Wolf 2017-05-23 18:38:20 +02:00
parent 664ba4d80e
commit dca3b3cd5f
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examples/osu035/example.v Normal file
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module top (input clk, input [7:0] a, b, output reg [15:0] c);
always @(posedge clk) c <= a * b;
endmodule