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Add test from #1144, and try reading without '-specify' flag

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This commit is contained in:
Eddie Hung 2019-06-28 10:12:48 -07:00
parent af74409749
commit dc677c791d
2 changed files with 16 additions and 0 deletions
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14
tests/various/specify.v
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@ -28,3 +28,17 @@ module test2 (
(B => Q) = 1.5; (B => Q) = 1.5;
endspecify endspecify
endmodule endmodule
module issue01144(input clk, d, output q);
specify
// Fails:
(posedge clk => (q +: d)) = (3,1);
(/*posedge*/ clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
(/*posedge*/ clk *> (q +: d)) = (3,1);
// Works:
(/*posedge*/ clk => q) = (3,1);
(/*posedge*/ clk *> q) = (3,1);
endspecify
endmodule

2
tests/various/specify.ys
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@ -54,3 +54,5 @@ equiv_struct
equiv_induct -seq 5 equiv_induct -seq 5
equiv_status -assert equiv_status -assert
design -reset design -reset
read_verilog specify.v