diff --git a/tests/various/specify.v b/tests/various/specify.v
index afc421da8..b1f399267 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -28,3 +28,17 @@ module test2 (
 		(B => Q) = 1.5;
 	endspecify
 endmodule
+
+module issue01144(input clk, d, output q);
+specify
+  // Fails:
+  (posedge clk => (q +: d)) = (3,1);
+  (/*posedge*/ clk => (q +: d)) = (3,1);
+  (posedge clk *> (q +: d)) = (3,1);
+  (/*posedge*/ clk *> (q +: d)) = (3,1);
+
+  // Works:
+  (/*posedge*/ clk => q) = (3,1);
+  (/*posedge*/ clk *> q) = (3,1);
+endspecify
+endmodule
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index a5ca07219..a2b6038e4 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -54,3 +54,5 @@ equiv_struct
 equiv_induct -seq 5
 equiv_status -assert
 design -reset
+
+read_verilog specify.v