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Revert "verilog: add support for SystemVerilog string literals."

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This reverts commit 5feb1a1752.
This commit is contained in:
Emil J. Tywoniak 2025-07-10 21:14:38 +02:00
parent e0822c048e
commit dc204dc909
4 changed files with 47 additions and 386 deletions
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tests/verilog/bug5160.v Normal file
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// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule