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docs: moving code examples

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Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin 2023-11-14 12:55:39 +13:00
parent 3d70867809
commit dbc38d72cf
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24
docs/source/yosys_internals/extensions.rst
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@ -26,22 +26,22 @@ The "stubsnets" example module
The following is the complete code of the "stubsnets" example module. It is
included in the Yosys source distribution as
``docs/source/CHAPTER_Prog/stubnets.cc``.
``docs/source/code_examples/stubnets/stubnets.cc``.
.. literalinclude:: ../CHAPTER_Prog/stubnets.cc
.. literalinclude:: /code_examples/stubnets/stubnets.cc
:language: c++
:linenos:
:caption: docs/source/CHAPTER_Prog/stubnets.cc
:caption: docs/source/code_examples/stubnets/stubnets.cc
.. literalinclude:: ../CHAPTER_Prog/Makefile
.. literalinclude:: /code_examples/stubnets/Makefile
:language: makefile
:linenos:
:caption: docs/source/CHAPTER_Prog/Makefile
:caption: docs/source/code_examples/stubnets/Makefile
.. literalinclude:: ../CHAPTER_Prog/test.v
.. literalinclude:: /code_examples/stubnets/test.v
:language: verilog
:linenos:
:caption: docs/source/CHAPTER_Prog/test.v
:caption: docs/source/code_examples/stubnets/test.v
Quick guide
-----------
@ -83,15 +83,13 @@ using these commands.
Creating modules from scratch
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. todo:: add/expand supporting text
.. todo:: add/expand supporting text, also use files in docs/resources/PRESENTATION_Prog
Let's create the following module using the RTLIL API:
.. code:: Verilog
module absval(input signed [3:0] a, output [3:0] y);
assign y = a[3] ? -a : a;
endmodule
.. literalinclude:: ../../resources/PRESENTATION_Prog/absval_ref.v
:language: Verilog
:caption: docs/resources/PRESENTATION_Prog/absval_ref.v
.. code:: C++