mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

docs: moving code examples

Browse source 
Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin 2023-11-14 12:55:39 +13:00
parent 3d70867809
commit dbc38d72cf
No known key found for this signature in database
119 changed files with 264 additions and 905 deletions
Download patch file Download diff file Expand all files Collapse all files

44
docs/source/using_yosys/more_scripting/interactive_investigation.rst
View file

@ -18,9 +18,9 @@ A simple circuit
:numref:`example_v` below provides the Verilog code for a simple circuit which
we will use to demonstrate the usage of :cmd:ref:`show` in a simple setting.
.. literalinclude:: /APPNOTE_011_Design_Investigation/example.v
.. literalinclude:: /code_examples/show/example.v
:language: Verilog
:caption: ``docs/source/APPNOTE_011_Design_Investigation/example.v``
:caption: ``docs/source/code_examples/show/example.v``
:name: example_v
The Yosys synthesis script we will be running is included as
@ -31,7 +31,7 @@ interactive shell to further investigate the circuit before continuing
synthesis.
.. code-block:: yoscrypt
:caption: ``docs/source/APPNOTE_011_Design_Investigation/example.ys``
:caption: ``docs/source/code_examples/show/example.ys``
:name: example_ys
read_verilog example.v
@ -115,8 +115,8 @@ Break-out boxes for signal vectors
The code listing below shows a simple circuit which uses a lot of spliced signal
accesses.
.. literalinclude:: /APPNOTE_011_Design_Investigation/splice.v
:caption: ``splice.v``
.. literalinclude:: /code_examples/show/splice.v
:caption: ``docs/source/code_examples/show/splice.v``
:name: splice_src
Notice how the output for this circuit from the :cmd:ref:`show` command
@ -341,20 +341,14 @@ a submodule. This has applications in synthesis scripts as well as in reverse
engineering and analysis. An example using :cmd:ref:`submod` is shown below for
reorganizing a module in Yosys and checking the resulting circuit.
.. literalinclude:: ../../../resources/PRESENTATION_ExOth/scrambler.v
.. literalinclude:: /code_examples/scrambler/scrambler.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/scrambler.v``
:caption: ``docs/source/code_examples/scrambler/scrambler.v``
.. code:: yoscrypt
read_verilog scrambler.v
hierarchy; proc;;
cd scrambler
submod -name xorshift32 \
xs %c %ci %D %c %ci:+[D] %D \
%ci*:-$dff xs %co %ci %d
.. literalinclude:: /code_examples/scrambler/scrambler.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/scrambler/scrambler.ys``
:end-before: cd ..
.. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
:class: width-helper
@ -446,17 +440,13 @@ smaller parts for viewing and working with. :numref:`submod` does exactly that,
utilising the :cmd:ref:`submod` command to split the circuit into three
sections: ``outstage``, ``selstage``, and ``scramble``.
.. code-block:: yoscrypt
:caption: The circuit from ``memdemo.v`` broken up using :cmd:ref:`submod`
.. literalinclude:: /code_examples/selections/submod.ys
:language: yoscrypt
:caption: Using :cmd:ref:`submod` to break up the circuit from ``memdemo.v``
:start-after: cd memdemo
:end-at: @selstage
:name: submod
select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
submod -name scramble @scramble
submod -name outstage @outstage
submod -name selstage @selstage
The ``-name`` option is used to specify the name of the new module and also the
name of the new cell in the current module. The resulting circuits are shown
below.
@ -584,7 +574,7 @@ value using the ``-set`` option. (Such a circuit that contains the circuit under
test plus additional constraint checking circuitry is called a ``miter``
circuit.)
.. literalinclude:: /APPNOTE_011_Design_Investigation/primetest.v
.. literalinclude:: /code_examples/primetest.v
:language: verilog
:caption: ``primetest.v``, a simple miter circuit for testing if a number is
prime. But it has a problem.

14
docs/source/using_yosys/more_scripting/selections.rst
View file

@ -103,7 +103,7 @@ processed it simply creates the union of all elements on the stack. So
:yoscrypt:`select t:$add a:foo` will select all ``$add`` cells and all objects
with the ``foo`` attribute set:
.. literalinclude:: /APPNOTE_011_Design_Investigation/foobaraddsub.v
.. literalinclude:: /code_examples/selections/foobaraddsub.v
:caption: Test module for operations on selections
:name: foobaraddsub
:language: verilog
@ -146,7 +146,7 @@ to set the attribute ``sumstuff`` on all cells generated by the first assign
statement. (This works on arbitrary large blocks of Verilog code an can be used
to mark portions of code for analysis.)
.. literalinclude:: /APPNOTE_011_Design_Investigation/sumprod.v
.. literalinclude:: /code_examples/selections/sumprod.v
:caption: Another test module for operations on selections
:name: sumprod
:language: verilog
@ -233,7 +233,7 @@ appended to the ``%ci`` action.
Lets consider :numref:`memdemo_src`. It serves no purpose other than being a
non-trivial circuit for demonstrating some of the advanced Yosys features.
.. literalinclude:: /APPNOTE_011_Design_Investigation/memdemo.v
.. literalinclude:: /code_examples/selections/memdemo.v
:caption: Demo circuit for demonstrating some advanced Yosys features
:name: memdemo_src
:language: verilog
@ -370,13 +370,13 @@ those cases selection variables must be used to capture more complex selections.
Example:
.. literalinclude:: ../../../resources/PRESENTATION_ExAdv/select.v
.. literalinclude:: /code_examples/selections/select.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/select.v``
:caption: ``docs/source/code_examples/selections/select.v``
.. literalinclude:: ../../../resources/PRESENTATION_ExAdv/select.ys
.. literalinclude:: /code_examples/selections/select.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExAdv/select.ys``
:caption: ``docs/source/code_examples/selections/select.ys``
:name: select_ys
.. figure:: /_images/res/PRESENTATION_ExAdv/select.*

79
docs/source/using_yosys/yosys_flows.rst
View file

@ -51,13 +51,13 @@ The extract pass
after `extract`
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test.v
.. literalinclude:: /code_examples/macc/macc_simple_test.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test.v``
:caption: ``docs/source/code_examples/macc/macc_simple_test.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_xmap.v
.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v``
:caption: ``docs/source/code_examples/macc/macc_simple_xmap.v``
.. code:: yoscrypt
@ -66,9 +66,9 @@ The extract pass
extract -map macc_simple_xmap.v;;
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_01.v
.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v``
:caption: ``docs/source/code_examples/macc/macc_simple_test_01.v``
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01a.*
:class: width-helper
@ -76,9 +76,9 @@ The extract pass
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01b.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_02.v
.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v``
:caption: ``docs/source/code_examples/macc/macc_simple_test_02.v``
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02a.*
:class: width-helper
@ -123,51 +123,51 @@ Make sure ``A`` is the smaller port on all multipliers
.. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_swap_map.v``
Wrapping multipliers: ``macc_xilinx_wrap_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 1-46
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_wrap_map.v``
Wrapping adders: ``macc_xilinx_wrap_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
:language: verilog
:lines: 48-89
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_wrap_map.v``
Extract: ``macc_xilinx_xmap.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v
.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_xmap.v``
... simply use the same wrapping commands on this module as on the design to
create a template for the :cmd:ref:`extract` command.
Unwrapping multipliers: ``macc_xilinx_unwrap_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 1-30
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_unwrap_map.v``
Unwrapping adders: ``macc_xilinx_unwrap_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
:language: verilog
:lines: 32-61
:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
:caption: ``docs/source/code_examples/macc/macc_xilinx_unwrap_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 1-6
:caption: ``test1`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
:caption: ``test1`` of ``docs/source/code_examples/macc/macc_xilinx_test.v``
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.*
:class: width-helper
@ -175,10 +175,10 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
:language: verilog
:lines: 8-13
:caption: ``test2`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
:caption: ``test2`` of ``docs/source/code_examples/macc/macc_xilinx_test.v``
.. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.*
:class: width-helper
@ -303,17 +303,17 @@ Checking techmap
Remember the following example from :doc:`/getting_started/typical_phases`?
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
:caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
.. literalinclude:: /code_examples/synth_flow/techmap_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
:caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
:caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
Lets see if it is correct..
@ -355,22 +355,17 @@ values for ``tready`` that yield the incorrect behavior.
.. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
.. literalinclude:: /code_examples/axis/axis_master.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``
:caption: ``docs/source/code_examples/axis/axis_master.v``
.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_test.v
.. literalinclude:: /code_examples/axis/axis_test.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/axis_test.v``
:caption: ``docs/source/code_examples/axis/axis_test.v``
.. code:: yoscrypt
read_verilog -sv axis_master.v axis_test.v
hierarchy -top axis_test
proc; flatten;;
sat -seq 50 -prove-asserts
.. literalinclude:: /code_examples/axis/axis_test.ys
:language: yoscrypt
:caption: ``docs/source/code_examples/axis/test.ys``
Result with unmodified ``axis_master.v``: