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docs: moving code examples

Browse source 
Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin 2023-11-14 12:55:39 +13:00
parent 3d70867809
commit dbc38d72cf
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119 changed files with 264 additions and 905 deletions
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22
docs/source/getting_started/examples.rst
View file

@ -53,13 +53,13 @@ Simple synthesis script
~~~~~~~~~~~~~~~~~~~~~~~
This section covers an example project available in
``docs/resources/PRESENTATION_Intro/*``. The project contains a simple ASIC
``docs/source/code_examples/intro/*``. The project contains a simple ASIC
synthesis script (``counter.ys``), a digital design written in Verilog
(``counter.v``), and a simple CMOS cell library (``mycells.lib``).
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
.. literalinclude:: /code_examples/intro/counter.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_Intro/counter.ys``
:caption: ``docs/source/code_examples/intro/counter.ys``
.. role:: yoscrypt(code)
:language: yoscrypt
@ -89,18 +89,18 @@ synthesis script (``counter.ys``), a digital design written in Verilog
Running the script
^^^^^^^^^^^^^^^^^^
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.v
.. literalinclude:: /code_examples/intro/counter.v
:language: Verilog
:caption: ``docs/resources/PRESENTATION_Intro/counter.v``
:caption: ``docs/source/code_examples/intro/counter.v``
.. literalinclude:: ../../resources/PRESENTATION_Intro/mycells.lib
.. literalinclude:: /code_examples/intro/mycells.lib
:language: Liberty
:caption: ``docs/resources/PRESENTATION_Intro/mycells.lib``
:caption: ``docs/source/code_examples/intro/mycells.lib``
Step 1
""""""
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
.. literalinclude:: /code_examples/intro/counter.ys
:language: yoscrypt
:lines: 1-3
@ -112,7 +112,7 @@ Result:
Step 2
""""""
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
.. literalinclude:: /code_examples/intro/counter.ys
:language: yoscrypt
:lines: 5-6
@ -124,7 +124,7 @@ Result:
Step 3
""""""
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
.. literalinclude:: /code_examples/intro/counter.ys
:language: yoscrypt
:lines: 8-9
@ -136,7 +136,7 @@ Result:
Step 4
""""""
.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
.. literalinclude:: /code_examples/intro/counter.ys
:language: yoscrypt
:lines: 11-18

92
docs/source/getting_started/typical_phases.rst
View file

@ -86,13 +86,13 @@ after design elaboration.
Example
^^^^^^^
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.v
.. literalinclude:: /code_examples/synth_flow/proc_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.v``
:caption: ``docs/source/code_examples/synth_flow/proc_01.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.ys
.. literalinclude:: /code_examples/synth_flow/proc_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.ys``
:caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
.. figure:: /_images/res/PRESENTATION_ExSyn/proc_01.*
:class: width-helper
@ -100,24 +100,24 @@ Example
.. figure:: /_images/res/PRESENTATION_ExSyn/proc_02.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.v
.. literalinclude:: /code_examples/synth_flow/proc_02.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.v``
:caption: ``docs/source/code_examples/synth_flow/proc_02.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.ys
.. literalinclude:: /code_examples/synth_flow/proc_02.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.ys``
:caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
.. figure:: /_images/res/PRESENTATION_ExSyn/proc_03.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.ys
.. literalinclude:: /code_examples/synth_flow/proc_03.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.ys``
:caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.v
.. literalinclude:: /code_examples/synth_flow/proc_03.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.v``
:caption: ``docs/source/code_examples/synth_flow/proc_03.v``
The :cmd:ref:`opt` command
@ -153,46 +153,46 @@ Example
.. figure:: /_images/res/PRESENTATION_ExSyn/opt_01.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.ys
.. literalinclude:: /code_examples/synth_flow/opt_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.ys``
:caption: ``docs/source/code_examples/synth_flow/opt_01.ys``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.v
.. literalinclude:: /code_examples/synth_flow/opt_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.v``
:caption: ``docs/source/code_examples/synth_flow/opt_01.v``
.. figure:: /_images/res/PRESENTATION_ExSyn/opt_02.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.ys
.. literalinclude:: /code_examples/synth_flow/opt_02.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.ys``
:caption: ``docs/source/code_examples/synth_flow/opt_02.ys``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.v
.. literalinclude:: /code_examples/synth_flow/opt_02.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.v``
:caption: ``docs/source/code_examples/synth_flow/opt_02.v``
.. figure:: /_images/res/PRESENTATION_ExSyn/opt_03.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.ys
.. literalinclude:: /code_examples/synth_flow/opt_03.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.ys``
:caption: ``docs/source/code_examples/synth_flow/opt_03.ys``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.v
.. literalinclude:: /code_examples/synth_flow/opt_03.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.v``
:caption: ``docs/source/code_examples/synth_flow/opt_03.v``
.. figure:: /_images/res/PRESENTATION_ExSyn/opt_04.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.v
.. literalinclude:: /code_examples/synth_flow/opt_04.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.v``
:caption: ``docs/source/code_examples/synth_flow/opt_04.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.ys
.. literalinclude:: /code_examples/synth_flow/opt_04.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.ys``
:caption: ``docs/source/code_examples/synth_flow/opt_04.ys``
When to use :cmd:ref:`opt` or :cmd:ref:`clean`
@ -249,24 +249,24 @@ Example
.. figure:: /_images/res/PRESENTATION_ExSyn/memory_01.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.ys
.. literalinclude:: /code_examples/synth_flow/memory_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.ys``
:caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.v
.. literalinclude:: /code_examples/synth_flow/memory_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.v``
:caption: ``docs/source/code_examples/synth_flow/memory_01.v``
.. figure:: /_images/res/PRESENTATION_ExSyn/memory_02.*
:class: width-helper
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.v
.. literalinclude:: /code_examples/synth_flow/memory_02.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.v``
:caption: ``docs/source/code_examples/synth_flow/memory_02.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.ys
.. literalinclude:: /code_examples/synth_flow/memory_02.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.ys``
:caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
The :cmd:ref:`fsm` command
@ -321,17 +321,17 @@ The :cmd:ref:`techmap` command
The :cmd:ref:`techmap` command replaces cells with implementations given as
verilog source. For example implementing a 32 bit adder using 16 bit adders:
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
:caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
.. literalinclude:: /code_examples/synth_flow/techmap_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
:caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
:caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
stdcell mapping
^^^^^^^^^^^^^^^
@ -378,13 +378,13 @@ advanced ABC features. It is also possible to write the design with
Example
^^^^^^^
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.v
.. literalinclude:: /code_examples/synth_flow/abc_01.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.v``
:caption: ``docs/source/code_examples/synth_flow/abc_01.v``
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.ys
.. literalinclude:: /code_examples/synth_flow/abc_01.ys
:language: yoscrypt
:caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.ys``
:caption: ``docs/source/code_examples/synth_flow/abc_01.ys``
.. figure:: /_images/res/PRESENTATION_ExSyn/abc_01.*
:class: width-helper