3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 18:15:34 +00:00

docs: moving code examples

Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin 2023-11-14 12:55:39 +13:00
parent 3d70867809
commit dbc38d72cf
No known key found for this signature in database
119 changed files with 264 additions and 905 deletions

View file

@ -0,0 +1,27 @@
module axis_master(aclk, aresetn, tvalid, tready, tdata);
input aclk, aresetn, tready;
output reg tvalid;
output reg [7:0] tdata;
reg [31:0] state;
always @(posedge aclk) begin
if (!aresetn) begin
state <= 314159265;
tvalid <= 0;
tdata <= 'bx;
end else begin
if (tvalid && tready)
tvalid <= 0;
if (!tvalid || !tready) begin
// ^- should not be inverted!
state = state ^ state << 13;
state = state ^ state >> 7;
state = state ^ state << 17;
if (state[9:8] == 0) begin
tvalid <= 1;
tdata <= state;
end
end
end
end
endmodule