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docs: moving code examples
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
This commit is contained in:
Krystine Sherwin
parent
3d70867809
commit
dbc38d72cf
119 changed files with 264 additions and 905 deletions
2
docs/resources/PRESENTATION_ExAdv/.gitignore
vendored
2
docs/resources/PRESENTATION_ExAdv/.gitignore
vendored
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@ -1,2 +0,0 @@
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*.dot
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*.pdf
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@ -1,31 +0,0 @@
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PROGRAM_PREFIX :=
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YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
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all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
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macc_simple_xmap.pdf macc_xilinx_xmap.pdf
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select.pdf: select.v select.ys
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$(YOSYS) select.ys
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red_or3x1.pdf: red_or3x1_*
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$(YOSYS) red_or3x1_test.ys
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sym_mul.pdf: sym_mul_*
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$(YOSYS) sym_mul_test.ys
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mymul.pdf: mymul_*
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$(YOSYS) mymul_test.ys
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mulshift.pdf: mulshift_*
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$(YOSYS) mulshift_test.ys
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addshift.pdf: addshift_*
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$(YOSYS) addshift_test.ys
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macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
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$(YOSYS) macc_simple_test.ys
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macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
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$(YOSYS) macc_xilinx_test.ys
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@ -1,20 +0,0 @@
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module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_BITS_CONNMAP_ = 0;
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parameter _TECHMAP_CONNMAP_A_ = 0;
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parameter _TECHMAP_CONNMAP_B_ = 0;
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wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
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_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
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assign Y = A << 1;
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endmodule
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@ -1,5 +0,0 @@
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module test (A, B, X, Y);
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input [7:0] A, B;
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output [7:0] X = A + B;
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output [7:0] Y = A + A;
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endmodule
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@ -1,6 +0,0 @@
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read_verilog addshift_test.v
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hierarchy -check -top test
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techmap -map addshift_map.v;;
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show -prefix addshift -format pdf -notitle
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@ -1,6 +0,0 @@
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module test(a, b, c, d, y);
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input [15:0] a, b;
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input [31:0] c, d;
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output [31:0] y;
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assign y = a * b + c + d;
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endmodule
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@ -1,37 +0,0 @@
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read_verilog macc_simple_test.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
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extract -constports -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_test_01.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
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extract -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_test_02.v
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hierarchy -check -top test;;
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show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
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extract -map macc_simple_xmap.v;;
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show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
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#################################################
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design -reset
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read_verilog macc_simple_xmap.v
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hierarchy -check -top macc_16_16_32;;
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show -prefix macc_simple_xmap -format pdf -notitle
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@ -1,6 +0,0 @@
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module test(a, b, c, d, x, y);
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input [15:0] a, b, c, d;
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input [31:0] x;
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output [31:0] y;
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assign y = a*b + c*d + x;
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endmodule
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@ -1,6 +0,0 @@
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module test(a, b, c, d, x, y);
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input [15:0] a, b, c, d;
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input [31:0] x;
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output [31:0] y;
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assign y = a*b + (c*d + x);
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endmodule
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@ -1,6 +0,0 @@
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module macc_16_16_32(a, b, c, y);
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input [15:0] a, b;
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input [31:0] c;
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output [31:0] y;
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assign y = a*b + c;
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endmodule
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@ -1,28 +0,0 @@
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(* techmap_celltype = "$mul" *)
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module mul_swap_ports (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
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\$mul #(
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.A_SIGNED(B_SIGNED),
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.B_SIGNED(A_SIGNED),
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.A_WIDTH(B_WIDTH),
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.B_WIDTH(A_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(B),
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.B(A),
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.Y(Y)
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);
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endmodule
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module test1(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + c*d + e*f;
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endmodule
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module test2(a, b, c, d, e, f, y);
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input [19:0] a, b, c;
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input [15:0] d, e, f;
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output [41:0] y;
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assign y = a*b + (c*d + e*f);
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endmodule
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@ -1,43 +0,0 @@
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read_verilog macc_xilinx_test.v
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read_verilog -lib -icells macc_xilinx_unwrap_map.v
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read_verilog -lib -icells macc_xilinx_xmap.v
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hierarchy -check ;;
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show -prefix macc_xilinx_test1a -format pdf -notitle test1
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show -prefix macc_xilinx_test2a -format pdf -notitle test2
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techmap -map macc_xilinx_swap_map.v;;
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show -prefix macc_xilinx_test1b -format pdf -notitle test1
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show -prefix macc_xilinx_test2b -format pdf -notitle test2
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
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-unsigned $__add_wrapper Y Y_WIDTH;;
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show -prefix macc_xilinx_test1c -format pdf -notitle test1
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show -prefix macc_xilinx_test2c -format pdf -notitle test2
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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show -prefix macc_xilinx_test1d -format pdf -notitle test1
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show -prefix macc_xilinx_test2d -format pdf -notitle test2
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techmap -map macc_xilinx_unwrap_map.v;;
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show -prefix macc_xilinx_test1e -format pdf -notitle test1
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show -prefix macc_xilinx_test2e -format pdf -notitle test2
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design -load __macc_xilinx_xmap
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show -prefix macc_xilinx_xmap -format pdf -notitle
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@ -1,61 +0,0 @@
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module \$__mul_wrapper (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [17:0] A;
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input [24:0] B;
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output [47:0] Y;
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wire [A_WIDTH-1:0] A_ORIG = A;
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wire [B_WIDTH-1:0] B_ORIG = B;
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wire [Y_WIDTH-1:0] Y_ORIG;
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assign Y = Y_ORIG;
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\$mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_ORIG),
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.B(B_ORIG),
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.Y(Y_ORIG)
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);
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endmodule
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module \$__add_wrapper (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [47:0] A;
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input [47:0] B;
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output [47:0] Y;
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wire [A_WIDTH-1:0] A_ORIG = A;
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wire [B_WIDTH-1:0] B_ORIG = B;
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wire [Y_WIDTH-1:0] Y_ORIG;
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assign Y = Y_ORIG;
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\$add #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_ORIG),
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.B(B_ORIG),
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.Y(Y_ORIG)
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);
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endmodule
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@ -1,89 +0,0 @@
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(* techmap_celltype = "$mul" *)
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module mul_wrap (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [17:0] A_18 = A;
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wire [24:0] B_25 = B;
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wire [47:0] Y_48;
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assign Y = Y_48;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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reg _TECHMAP_FAIL_;
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initial begin
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_TECHMAP_FAIL_ <= 0;
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if (A_SIGNED || B_SIGNED)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH < 4 || B_WIDTH < 4)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH > 18 || B_WIDTH > 25)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH*B_WIDTH < 100)
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_TECHMAP_FAIL_ <= 1;
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end
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\$__mul_wrapper #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_18),
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.B(B_25),
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.Y(Y_48)
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);
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endmodule
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(* techmap_celltype = "$add" *)
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module add_wrap (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [47:0] A_48 = A;
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wire [47:0] B_48 = B;
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wire [47:0] Y_48;
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assign Y = Y_48;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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reg _TECHMAP_FAIL_;
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initial begin
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_TECHMAP_FAIL_ <= 0;
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if (A_SIGNED || B_SIGNED)
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_TECHMAP_FAIL_ <= 1;
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if (A_WIDTH < 10 && B_WIDTH < 10)
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_TECHMAP_FAIL_ <= 1;
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end
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\$__add_wrapper #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_48),
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.B(B_48),
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.Y(Y_48)
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);
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endmodule
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@ -1,10 +0,0 @@
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module DSP48_MACC (a, b, c, y);
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input [17:0] a;
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input [24:0] b;
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input [47:0] c;
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output [47:0] y;
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assign y = a*b + c;
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endmodule
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@ -1,26 +0,0 @@
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module MYMUL(A, B, Y);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output reg [WIDTH-1:0] Y;
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parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
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parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
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reg _TECHMAP_FAIL_;
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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integer i;
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always @* begin
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_TECHMAP_FAIL_ <= 1;
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for (i = 0; i < WIDTH; i=i+1) begin
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if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
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_TECHMAP_FAIL_ <= 0;
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Y <= B << i;
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end
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if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
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_TECHMAP_FAIL_ <= 0;
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Y <= A << i;
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end
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||||
end
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||||
end
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endmodule
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@ -1,5 +0,0 @@
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module test (A, X, Y);
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input [7:0] A;
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output [7:0] X = A * 8'd 6;
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output [7:0] Y = A * 8'd 8;
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endmodule
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@ -1,7 +0,0 @@
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read_verilog mulshift_test.v
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hierarchy -check -top test
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||||
techmap -map sym_mul_map.v \
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-map mulshift_map.v;;
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|
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show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v
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|
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@ -1,15 +0,0 @@
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module MYMUL(A, B, Y);
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parameter WIDTH = 1;
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input [WIDTH-1:0] A, B;
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output reg [WIDTH-1:0] Y;
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|
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wire [1023:0] _TECHMAP_DO_ = "proc; clean";
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|
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integer i;
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always @* begin
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Y = 0;
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for (i = 0; i < WIDTH; i=i+1)
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if (A[i])
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Y = Y + (B << i);
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||||
end
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||||
endmodule
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|
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@ -1,4 +0,0 @@
|
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module test(A, B, Y);
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input [1:0] A, B;
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output [1:0] Y = A * B;
|
||||
endmodule
|
||||
|
|
@ -1,15 +0,0 @@
|
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read_verilog mymul_test.v
|
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hierarchy -check -top test
|
||||
|
||||
techmap -map sym_mul_map.v \
|
||||
-map mymul_map.v;;
|
||||
|
||||
rename test test_mapped
|
||||
read_verilog mymul_test.v
|
||||
miter -equiv test test_mapped miter
|
||||
flatten miter
|
||||
|
||||
sat -verify -prove trigger 0 miter
|
||||
|
||||
splitnets -ports test_mapped/A
|
||||
show -prefix mymul -format pdf -notitle test_mapped
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
module OR3X1(A, B, C, Y);
|
||||
input A, B, C;
|
||||
output Y;
|
||||
assign Y = A | B | C;
|
||||
endmodule
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
module \$reduce_or (A, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
function integer min;
|
||||
input integer a, b;
|
||||
begin
|
||||
if (a < b)
|
||||
min = a;
|
||||
else
|
||||
min = b;
|
||||
end
|
||||
endfunction
|
||||
|
||||
genvar i;
|
||||
generate begin
|
||||
if (A_WIDTH == 0) begin
|
||||
assign Y = 0;
|
||||
end
|
||||
if (A_WIDTH == 1) begin
|
||||
assign Y = A;
|
||||
end
|
||||
if (A_WIDTH == 2) begin
|
||||
wire ybuf;
|
||||
OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
|
||||
assign Y = ybuf;
|
||||
end
|
||||
if (A_WIDTH == 3) begin
|
||||
wire ybuf;
|
||||
OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
|
||||
assign Y = ybuf;
|
||||
end
|
||||
if (A_WIDTH > 3) begin
|
||||
localparam next_stage_sz = (A_WIDTH+2) / 3;
|
||||
wire [next_stage_sz-1:0] next_stage;
|
||||
for (i = 0; i < next_stage_sz; i = i+1) begin
|
||||
localparam bits = min(A_WIDTH - 3*i, 3);
|
||||
assign next_stage[i] = |A[3*i +: bits];
|
||||
end
|
||||
assign Y = |next_stage;
|
||||
end
|
||||
end endgenerate
|
||||
endmodule
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
module test (A, Y);
|
||||
input [6:0] A;
|
||||
output Y;
|
||||
assign Y = |A;
|
||||
endmodule
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
read_verilog red_or3x1_test.v
|
||||
hierarchy -check -top test
|
||||
|
||||
techmap -map red_or3x1_map.v;;
|
||||
|
||||
splitnets -ports
|
||||
show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
module test(clk, s, a, y);
|
||||
input clk, s;
|
||||
input [15:0] a;
|
||||
output [15:0] y;
|
||||
reg [15:0] b, c;
|
||||
|
||||
always @(posedge clk) begin
|
||||
b <= a;
|
||||
c <= b;
|
||||
end
|
||||
|
||||
wire [15:0] state_a = (a ^ b) + c;
|
||||
wire [15:0] state_b = (a ^ b) - c;
|
||||
assign y = !s ? state_a : state_b;
|
||||
endmodule
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
read_verilog select.v
|
||||
hierarchy -check -top test
|
||||
proc; opt
|
||||
cd test
|
||||
select -set cone_a state_a %ci*:-$dff
|
||||
select -set cone_b state_b %ci*:-$dff
|
||||
select -set cone_ab @cone_a @cone_b %i
|
||||
show -prefix select -format pdf -notitle \
|
||||
-color red @cone_ab -color magenta @cone_a \
|
||||
-color blue @cone_b
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
module MYMUL(A, B, Y);
|
||||
parameter WIDTH = 1;
|
||||
input [WIDTH-1:0] A, B;
|
||||
output [WIDTH-1:0] Y;
|
||||
assign Y = A * B;
|
||||
endmodule
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
module \$mul (A, B, Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter B_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
|
||||
|
||||
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
|
||||
endmodule
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
module test(A, B, C, Y1, Y2);
|
||||
input [7:0] A, B, C;
|
||||
output [7:0] Y1 = A * B;
|
||||
output [15:0] Y2 = A * C;
|
||||
endmodule
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
read_verilog sym_mul_test.v
|
||||
hierarchy -check -top test
|
||||
|
||||
techmap -map sym_mul_map.v;;
|
||||
|
||||
show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v
|
||||
3
docs/resources/PRESENTATION_ExOth/.gitignore
vendored
3
docs/resources/PRESENTATION_ExOth/.gitignore
vendored
|
|
@ -1,3 +0,0 @@
|
|||
*.dot
|
||||
*.pdf
|
||||
*.log
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
PROGRAM_PREFIX :=
|
||||
|
||||
YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
|
||||
|
||||
all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log
|
||||
|
||||
scrambler_p01.pdf: scrambler.ys scrambler.v
|
||||
$(YOSYS) scrambler.ys
|
||||
|
||||
scrambler_p02.pdf: scrambler_p01.pdf
|
||||
|
||||
equiv.log: equiv.ys
|
||||
$(YOSYS) -l equiv.log_new equiv.ys
|
||||
mv equiv.log_new equiv.log
|
||||
|
||||
axis_test.log: axis_test.ys axis_master.v axis_test.v
|
||||
$(YOSYS) -l axis_test.log_new axis_test.ys
|
||||
mv axis_test.log_new axis_test.log
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
module axis_master(aclk, aresetn, tvalid, tready, tdata);
|
||||
input aclk, aresetn, tready;
|
||||
output reg tvalid;
|
||||
output reg [7:0] tdata;
|
||||
|
||||
reg [31:0] state;
|
||||
always @(posedge aclk) begin
|
||||
if (!aresetn) begin
|
||||
state <= 314159265;
|
||||
tvalid <= 0;
|
||||
tdata <= 'bx;
|
||||
end else begin
|
||||
if (tvalid && tready)
|
||||
tvalid <= 0;
|
||||
if (!tvalid || !tready) begin
|
||||
// ^- should not be inverted!
|
||||
state = state ^ state << 13;
|
||||
state = state ^ state >> 7;
|
||||
state = state ^ state << 17;
|
||||
if (state[9:8] == 0) begin
|
||||
tvalid <= 1;
|
||||
tdata <= state;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
module axis_test(aclk, tready);
|
||||
input aclk, tready;
|
||||
wire aresetn, tvalid;
|
||||
wire [7:0] tdata;
|
||||
|
||||
integer counter = 0;
|
||||
reg aresetn = 0;
|
||||
|
||||
axis_master uut (aclk, aresetn, tvalid, tready, tdata);
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (aresetn && tready && tvalid) begin
|
||||
if (counter == 0) assert(tdata == 19);
|
||||
if (counter == 1) assert(tdata == 99);
|
||||
if (counter == 2) assert(tdata == 1);
|
||||
if (counter == 3) assert(tdata == 244);
|
||||
if (counter == 4) assert(tdata == 133);
|
||||
if (counter == 5) assert(tdata == 209);
|
||||
if (counter == 6) assert(tdata == 241);
|
||||
if (counter == 7) assert(tdata == 137);
|
||||
if (counter == 8) assert(tdata == 176);
|
||||
if (counter == 9) assert(tdata == 6);
|
||||
counter <= counter + 1;
|
||||
end
|
||||
aresetn <= 1;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
read_verilog -sv axis_master.v axis_test.v
|
||||
hierarchy -top axis_test
|
||||
|
||||
proc; flatten;;
|
||||
sat -falsify -seq 50 -prove-asserts
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
# read test design
|
||||
read_verilog ../PRESENTATION_ExSyn/techmap_01.v
|
||||
hierarchy -top test
|
||||
|
||||
# create two version of the design: test_orig and test_mapped
|
||||
copy test test_orig
|
||||
rename test test_mapped
|
||||
|
||||
# apply the techmap only to test_mapped
|
||||
techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
|
||||
|
||||
# create a miter circuit to test equivalence
|
||||
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
|
||||
flatten miter
|
||||
|
||||
# run equivalence check
|
||||
sat -verify -prove-asserts -show-inputs -show-outputs miter
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
module scrambler(
|
||||
input clk, rst, in_bit,
|
||||
output reg out_bit
|
||||
);
|
||||
reg [31:0] xs;
|
||||
always @(posedge clk) begin
|
||||
if (rst)
|
||||
xs = 1;
|
||||
xs = xs ^ (xs << 13);
|
||||
xs = xs ^ (xs >> 17);
|
||||
xs = xs ^ (xs << 5);
|
||||
out_bit <= in_bit ^ xs[0];
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
|
||||
read_verilog scrambler.v
|
||||
|
||||
hierarchy; proc;;
|
||||
|
||||
cd scrambler
|
||||
submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
|
||||
cd ..
|
||||
|
||||
show -prefix scrambler_p01 -format pdf -notitle scrambler
|
||||
show -prefix scrambler_p02 -format pdf -notitle xorshift32
|
||||
|
||||
echo on
|
||||
|
||||
cd xorshift32
|
||||
rename n2 in
|
||||
rename n1 out
|
||||
|
||||
eval -set in 1 -show out
|
||||
eval -set in 270369 -show out
|
||||
|
||||
sat -set out 632435482
|
||||
|
||||
2
docs/resources/PRESENTATION_ExSyn/.gitignore
vendored
2
docs/resources/PRESENTATION_ExSyn/.gitignore
vendored
|
|
@ -1,2 +0,0 @@
|
|||
*.dot
|
||||
*.pdf
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
|
||||
TARGETS += proc_01 proc_02 proc_03
|
||||
TARGETS += opt_01 opt_02 opt_03 opt_04
|
||||
TARGETS += memory_01 memory_02
|
||||
TARGETS += techmap_01
|
||||
TARGETS += abc_01
|
||||
|
||||
PROGRAM_PREFIX :=
|
||||
|
||||
YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
|
||||
|
||||
all: $(addsuffix .pdf,$(TARGETS))
|
||||
|
||||
define make_pdf_template
|
||||
$(1).pdf: $(1)*.v $(1)*.ys
|
||||
$(YOSYS) -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
|
||||
endef
|
||||
|
||||
$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
|
||||
|
||||
clean:
|
||||
rm -f $(addsuffix .pdf,$(TARGETS))
|
||||
rm -f $(addsuffix .dot,$(TARGETS))
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
module test(input clk, a, b, c,
|
||||
output reg y);
|
||||
|
||||
reg [2:0] q1, q2;
|
||||
always @(posedge clk) begin
|
||||
q1 <= { a, b, c };
|
||||
q2 <= q1;
|
||||
y <= ^q2;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
read_verilog abc_01.v
|
||||
read_verilog -lib abc_01_cells.v
|
||||
hierarchy -check -top test
|
||||
proc; opt; techmap
|
||||
abc -dff -liberty abc_01_cells.lib;;
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
// test comment
|
||||
/* test comment */
|
||||
library(demo) {
|
||||
cell(BUF) {
|
||||
area: 6;
|
||||
pin(A) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "A"; }
|
||||
}
|
||||
cell(NOT) {
|
||||
area: 3;
|
||||
pin(A) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "A'"; }
|
||||
}
|
||||
cell(NAND) {
|
||||
area: 4;
|
||||
pin(A) { direction: input; }
|
||||
pin(B) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "(A*B)'"; }
|
||||
}
|
||||
cell(NOR) {
|
||||
area: 4;
|
||||
pin(A) { direction: input; }
|
||||
pin(B) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "(A+B)'"; }
|
||||
}
|
||||
cell(DFF) {
|
||||
area: 18;
|
||||
ff(IQ, IQN) { clocked_on: C;
|
||||
next_state: D; }
|
||||
pin(C) { direction: input;
|
||||
clock: true; }
|
||||
pin(D) { direction: input; }
|
||||
pin(Q) { direction: output;
|
||||
function: "IQ"; }
|
||||
}
|
||||
cell(DFFSR) {
|
||||
area: 18;
|
||||
ff(IQ, IQN) { clocked_on: C;
|
||||
next_state: D;
|
||||
preset: S;
|
||||
clear: R; }
|
||||
pin(C) { direction: input;
|
||||
clock: true; }
|
||||
pin(D) { direction: input; }
|
||||
pin(Q) { direction: output;
|
||||
function: "IQ"; }
|
||||
pin(S) { direction: input; }
|
||||
pin(R) { direction: input; }
|
||||
}
|
||||
}
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
|
||||
module BUF(A, Y);
|
||||
input A;
|
||||
output Y = A;
|
||||
endmodule
|
||||
|
||||
module NOT(A, Y);
|
||||
input A;
|
||||
output Y = ~A;
|
||||
endmodule
|
||||
|
||||
module NAND(A, B, Y);
|
||||
input A, B;
|
||||
output Y = ~(A & B);
|
||||
endmodule
|
||||
|
||||
module NOR(A, B, Y);
|
||||
input A, B;
|
||||
output Y = ~(A | B);
|
||||
endmodule
|
||||
|
||||
module DFF(C, D, Q);
|
||||
input C, D;
|
||||
output reg Q;
|
||||
always @(posedge C)
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
||||
module DFFSR(C, D, Q, S, R);
|
||||
input C, D, S, R;
|
||||
output reg Q;
|
||||
always @(posedge C, posedge S, posedge R)
|
||||
if (S)
|
||||
Q <= 1'b1;
|
||||
else if (R)
|
||||
Q <= 1'b0;
|
||||
else
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
module test(input CLK, ADDR,
|
||||
input [7:0] DIN,
|
||||
output reg [7:0] DOUT);
|
||||
reg [7:0] mem [0:1];
|
||||
always @(posedge CLK) begin
|
||||
mem[ADDR] <= DIN;
|
||||
DOUT <= mem[ADDR];
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog memory_01.v
|
||||
hierarchy -check -top test
|
||||
proc;; memory; opt
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
module test(
|
||||
input WR1_CLK, WR2_CLK,
|
||||
input WR1_WEN, WR2_WEN,
|
||||
input [7:0] WR1_ADDR, WR2_ADDR,
|
||||
input [7:0] WR1_DATA, WR2_DATA,
|
||||
input RD1_CLK, RD2_CLK,
|
||||
input [7:0] RD1_ADDR, RD2_ADDR,
|
||||
output reg [7:0] RD1_DATA, RD2_DATA
|
||||
);
|
||||
|
||||
reg [7:0] memory [0:255];
|
||||
|
||||
always @(posedge WR1_CLK)
|
||||
if (WR1_WEN)
|
||||
memory[WR1_ADDR] <= WR1_DATA;
|
||||
|
||||
always @(posedge WR2_CLK)
|
||||
if (WR2_WEN)
|
||||
memory[WR2_ADDR] <= WR2_DATA;
|
||||
|
||||
always @(posedge RD1_CLK)
|
||||
RD1_DATA <= memory[RD1_ADDR];
|
||||
|
||||
always @(posedge RD2_CLK)
|
||||
RD2_DATA <= memory[RD2_ADDR];
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
read_verilog memory_02.v
|
||||
hierarchy -check -top test
|
||||
proc;; memory -nomap
|
||||
opt -mux_undef -mux_bool
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
module test(input A, B, output Y);
|
||||
assign Y = A ? A ? B : 1'b1 : B;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog opt_01.v
|
||||
hierarchy -check -top test
|
||||
opt
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
module test(input A, output Y, Z);
|
||||
assign Y = A == A, Z = A != A;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog opt_02.v
|
||||
hierarchy -check -top test
|
||||
opt
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
module test(input [3:0] A, B,
|
||||
output [3:0] Y, Z);
|
||||
assign Y = A + B, Z = B + A;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog opt_03.v
|
||||
hierarchy -check -top test
|
||||
opt
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
module test(input CLK, ARST,
|
||||
output [7:0] Q1, Q2, Q3);
|
||||
|
||||
wire NO_CLK = 0;
|
||||
|
||||
always @(posedge CLK, posedge ARST)
|
||||
if (ARST)
|
||||
Q1 <= 42;
|
||||
|
||||
always @(posedge NO_CLK, posedge ARST)
|
||||
if (ARST)
|
||||
Q2 <= 42;
|
||||
else
|
||||
Q2 <= 23;
|
||||
|
||||
always @(posedge CLK)
|
||||
Q3 <= 42;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog opt_04.v
|
||||
hierarchy -check -top test
|
||||
proc; opt
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
module test(input D, C, R, output reg Q);
|
||||
always @(posedge C, posedge R)
|
||||
if (R)
|
||||
Q <= 0;
|
||||
else
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog proc_01.v
|
||||
hierarchy -check -top test
|
||||
proc;;
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
module test(input D, C, R, RV,
|
||||
output reg Q);
|
||||
always @(posedge C, posedge R)
|
||||
if (R)
|
||||
Q <= RV;
|
||||
else
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog proc_02.v
|
||||
hierarchy -check -top test
|
||||
proc;;
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
module test(input A, B, C, D, E,
|
||||
output reg Y);
|
||||
always @* begin
|
||||
Y <= A;
|
||||
if (B)
|
||||
Y <= C;
|
||||
if (D)
|
||||
Y <= E;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog proc_03.v
|
||||
hierarchy -check -top test
|
||||
proc;;
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
module test(input [31:0] a, b,
|
||||
output [31:0] y);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
read_verilog techmap_01.v
|
||||
hierarchy -check -top test
|
||||
techmap -map techmap_01_map.v;;
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
module \$add (A, B, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter B_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
generate
|
||||
if ((A_WIDTH == 32) && (B_WIDTH == 32))
|
||||
begin
|
||||
wire [16:0] S1 = A[15:0] + B[15:0];
|
||||
wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
|
||||
assign Y = {S2[15:0], S1[15:0]};
|
||||
end
|
||||
else
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
8
docs/resources/PRESENTATION_Intro/.gitignore
vendored
8
docs/resources/PRESENTATION_Intro/.gitignore
vendored
|
|
@ -1,8 +0,0 @@
|
|||
counter_00.dot
|
||||
counter_01.dot
|
||||
counter_02.dot
|
||||
counter_03.dot
|
||||
counter_00.pdf
|
||||
counter_01.pdf
|
||||
counter_02.pdf
|
||||
counter_03.pdf
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
PROGRAM_PREFIX :=
|
||||
|
||||
YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
|
||||
|
||||
all: counter_00.dot counter_01.dot counter_02.dot counter_03.dot
|
||||
|
||||
counter_00.dot: counter.v counter.ys mycells.lib
|
||||
$(YOSYS) counter_outputs.ys
|
||||
|
||||
counter_01.dot: counter_00.dot
|
||||
counter_02.dot: counter_00.dot
|
||||
counter_03.dot: counter_00.dot
|
||||
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
module counter (clk, rst, en, count);
|
||||
|
||||
input clk, rst, en;
|
||||
output reg [1:0] count;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
count <= 2'd0;
|
||||
else if (en)
|
||||
count <= count + 2'd1;
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
# read design
|
||||
read_verilog counter.v
|
||||
hierarchy -check -top counter
|
||||
|
||||
# the high-level stuff
|
||||
proc; opt; memory; opt; fsm; opt
|
||||
|
||||
# mapping to internal cell library
|
||||
techmap; opt
|
||||
|
||||
# mapping flip-flops to mycells.lib
|
||||
dfflibmap -liberty mycells.lib
|
||||
|
||||
# mapping logic to mycells.lib
|
||||
abc -liberty mycells.lib
|
||||
|
||||
# cleanup
|
||||
clean
|
||||
|
||||
# write synthesized design
|
||||
write_verilog synth.v
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
# read design
|
||||
read_verilog counter.v
|
||||
hierarchy -check -top counter
|
||||
|
||||
show -notitle -format dot -prefix counter_00
|
||||
|
||||
# the high-level stuff
|
||||
proc; opt; memory; opt; fsm; opt
|
||||
|
||||
show -notitle -format dot -prefix counter_01
|
||||
|
||||
# mapping to internal cell library
|
||||
techmap; opt
|
||||
|
||||
splitnets -ports;;
|
||||
show -notitle -format dot -prefix counter_02
|
||||
|
||||
# mapping flip-flops to mycells.lib
|
||||
dfflibmap -liberty mycells.lib
|
||||
|
||||
# mapping logic to mycells.lib
|
||||
abc -liberty mycells.lib
|
||||
|
||||
# cleanup
|
||||
clean
|
||||
|
||||
show -notitle -lib mycells.v -format dot -prefix counter_03
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
library(demo) {
|
||||
cell(BUF) {
|
||||
area: 6;
|
||||
pin(A) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "A"; }
|
||||
}
|
||||
cell(NOT) {
|
||||
area: 3;
|
||||
pin(A) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "A'"; }
|
||||
}
|
||||
cell(NAND) {
|
||||
area: 4;
|
||||
pin(A) { direction: input; }
|
||||
pin(B) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "(A*B)'"; }
|
||||
}
|
||||
cell(NOR) {
|
||||
area: 4;
|
||||
pin(A) { direction: input; }
|
||||
pin(B) { direction: input; }
|
||||
pin(Y) { direction: output;
|
||||
function: "(A+B)'"; }
|
||||
}
|
||||
cell(DFF) {
|
||||
area: 18;
|
||||
ff(IQ, IQN) { clocked_on: C;
|
||||
next_state: D; }
|
||||
pin(C) { direction: input;
|
||||
clock: true; }
|
||||
pin(D) { direction: input; }
|
||||
pin(Q) { direction: output;
|
||||
function: "IQ"; }
|
||||
}
|
||||
}
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
|
||||
module NOT(A, Y);
|
||||
input A;
|
||||
output Y = ~A;
|
||||
endmodule
|
||||
|
||||
module NAND(A, B, Y);
|
||||
input A, B;
|
||||
output Y = ~(A & B);
|
||||
endmodule
|
||||
|
||||
module NOR(A, B, Y);
|
||||
input A, B;
|
||||
output Y = ~(A | B);
|
||||
endmodule
|
||||
|
||||
module DFF(C, D, Q);
|
||||
input C, D;
|
||||
output reg Q;
|
||||
always @(posedge C)
|
||||
Q <= D;
|
||||
endmodule
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue