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Use selection helpers

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Catch more uses of selection constructor without assigning a design.
This commit is contained in:
Krystine Sherwin 2025-03-14 14:08:13 +13:00
parent a67b57bd64
commit dac2bb7d4d
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23 changed files with 84 additions and 78 deletions
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2
passes/cmds/add.cc
View file

@ -102,7 +102,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
RTLIL::Module *mod = design->module(cell->type);
if (mod == nullptr)
continue;
if (!design->selected_whole_module(mod->name))
if (!mod->is_selected_whole())
continue;
if (mod->get_blackbox_attribute())
continue;

6
passes/cmds/design.cc
View file

@ -216,8 +216,8 @@ struct DesignPass : public Pass {
RTLIL::Selection sel;
if (argidx != args.size()) {
handle_extra_select_args(this, args, argidx, args.size(), copy_from_design);
sel = copy_from_design->selection_stack.back();
copy_from_design->selection_stack.pop_back();
sel = copy_from_design->selection();
copy_from_design->pop_selection();
argidx = args.size();
}
@ -368,7 +368,7 @@ struct DesignPass : public Pass {
design->selection_vars.clear();
design->selected_active_module.clear();
design->selection_stack.push_back(RTLIL::Selection());
design->push_full_selection();
}
if (reset_mode || reset_vlog_mode || !load_name.empty() || push_mode || pop_mode)

2
passes/cmds/scc.cc
View file

@ -340,7 +340,7 @@ struct SccPass : public Pass {
int origSelectPos = design->selection_stack.size() - 1;
extra_args(args, argidx, design);
RTLIL::Selection newSelection(false);
RTLIL::Selection newSelection(false, false, design);
int scc_counter = 0;
for (auto mod : design->selected_modules())

60
passes/cmds/select.cc
View file

@ -687,7 +687,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
if (arg[0] == '%') {
if (arg == "%") {
if (design->selection_stack.size() > 0)
work_stack.push_back(design->selection_stack.back());
work_stack.push_back(design->selection());
} else
if (arg == "%%") {
while (work_stack.size() > 1) {
@ -1031,9 +1031,9 @@ void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t arg
work_stack.pop_back();
}
if (work_stack.empty())
design->selection_stack.push_back(RTLIL::Selection(false, false, design));
design->push_empty_selection();
else
design->selection_stack.push_back(work_stack.back());
design->push_selection(work_stack.back());
}
// extern decl. in register.h
@ -1420,7 +1420,7 @@ struct SelectPass : public Pass {
if (f.fail())
log_error("Can't open '%s' for reading: %s\n", read_file.c_str(), strerror(errno));
RTLIL::Selection sel(false);
RTLIL::Selection sel(false, false, design);
string line;
while (std::getline(f, line)) {
@ -1461,7 +1461,7 @@ struct SelectPass : public Pass {
log_cmd_error("Option -unset can not be combined with -list, -write, -count, -set, %s.\n", common_flagset);
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
RTLIL::Selection sel(true, false, design);
select_filter_active_mod(design, sel);
work_stack.push_back(sel);
}
@ -1474,13 +1474,15 @@ struct SelectPass : public Pass {
log_assert(design->selection_stack.size() > 0);
if (clear_mode) {
design->selection_stack.back() = RTLIL::Selection(true, false, design);
design->pop_selection();
design->push_full_selection();
design->selected_active_module = std::string();
return;
}
if (none_mode) {
design->selection_stack.back() = RTLIL::Selection(false, false, design);
design->pop_selection();
design->push_empty_selection();
return;
}
@ -1496,8 +1498,8 @@ struct SelectPass : public Pass {
log_error("Can't open '%s' for writing: %s\n", write_file.c_str(), strerror(errno));
}
if (work_stack.size() > 0)
design->selection_stack.push_back(work_stack.back());
RTLIL::Selection *sel = &design->selection_stack.back();
design->push_selection(work_stack.back());
RTLIL::Selection *sel = &design->selection();
sel->optimize(design);
for (auto mod : design->selected_modules())
{
@ -1515,7 +1517,7 @@ struct SelectPass : public Pass {
if (f != nullptr)
fclose(f);
if (work_stack.size() > 0)
design->selection_stack.pop_back();
design->pop_selection();
#undef LOG_OBJECT
return;
}
@ -1524,8 +1526,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to add to selection.\n");
select_op_union(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
select_op_union(design, design->selection(), work_stack.back());
design->selection().optimize(design);
return;
}
@ -1533,8 +1535,8 @@ struct SelectPass : public Pass {
{
if (work_stack.size() == 0)
log_cmd_error("Nothing to delete from selection.\n");
select_op_diff(design, design->selection_stack.back(), work_stack.back());
design->selection_stack.back().optimize(design);
select_op_diff(design, design->selection(), work_stack.back());
design->selection().optimize(design);
return;
}
@ -1574,7 +1576,7 @@ struct SelectPass : public Pass {
if (work_stack.size() == 0)
log_cmd_error("No selection to check.\n");
RTLIL::Selection *sel = &work_stack.back();
design->selection_stack.push_back(*sel);
design->push_selection(*sel);
sel->optimize(design);
for (auto mod : design->selected_modules()) {
module_count++;
@ -1604,7 +1606,7 @@ struct SelectPass : public Pass {
log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
total_count, assert_min, sel_str.c_str(), desc.c_str());
}
design->selection_stack.pop_back();
design->pop_selection();
return;
}
@ -1625,7 +1627,7 @@ struct SelectPass : public Pass {
}
if (work_stack.size() == 0) {
RTLIL::Selection &sel = design->selection_stack.back();
RTLIL::Selection &sel = design->selection();
if (sel.full_selection)
log("*\n");
for (auto &it : sel.selected_modules)
@ -1636,8 +1638,8 @@ struct SelectPass : public Pass {
return;
}
design->selection_stack.back() = work_stack.back();
design->selection_stack.back().optimize(design);
design->selection() = work_stack.back();
design->selection().optimize(design);
}
} SelectPass;
@ -1677,7 +1679,8 @@ struct CdPass : public Pass {
log_cmd_error("Invalid number of arguments.\n");
if (args.size() == 1 || args[1] == "/") {
design->selection_stack.back() = RTLIL::Selection(true, false, design);
design->pop_selection();
design->push_full_selection();
design->selected_active_module = std::string();
return;
}
@ -1686,7 +1689,8 @@ struct CdPass : public Pass {
{
string modname = design->selected_active_module;
design->selection_stack.back() = RTLIL::Selection(true, false, design);
design->pop_selection();
design->push_full_selection();
design->selected_active_module = std::string();
while (1)
@ -1703,9 +1707,10 @@ struct CdPass : public Pass {
continue;
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection(true, false, design);
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
return;
}
@ -1722,9 +1727,10 @@ struct CdPass : public Pass {
if (design->module(modname) != nullptr) {
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection(true, false, design);
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
design->pop_selection();
design->push_full_selection();
select_filter_active_mod(design, design->selection());
design->selection().optimize(design);
return;
}

8
passes/cmds/show.cc
View file

@ -802,8 +802,8 @@ struct ShowPass : public Pass {
std::pair<std::string, RTLIL::Selection> data;
data.first = args[++argidx], argidx++;
handle_extra_select_args(this, args, argidx, argidx+1, design);
data.second = design->selection_stack.back();
design->selection_stack.pop_back();
data.second = design->selection();
design->pop_selection();
color_selections.push_back(data);
continue;
}
@ -811,8 +811,8 @@ struct ShowPass : public Pass {
std::pair<std::string, RTLIL::Selection> data;
data.first = args[++argidx], argidx++;
handle_extra_select_args(this, args, argidx, argidx+1, design);
data.second = design->selection_stack.back();
design->selection_stack.pop_back();
data.second = design->selection();
design->pop_selection();
label_selections.push_back(data);
continue;
}

2
passes/cmds/stat.cc
View file

@ -468,7 +468,7 @@ struct StatPass : public Pass {
first_module = false;
} else {
log("\n");
log("=== %s%s ===\n", log_id(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)");
log("=== %s%s ===\n", log_id(mod->name), mod->is_selected_whole() ? "" : " (partially selected)");
log("\n");
data.log_data(mod->name, false);
}

4
passes/cmds/viz.cc
View file

@ -950,8 +950,8 @@ struct VizPass : public Pass {
auto type = arg == "-g" || arg == "-G" ? VizConfig::TYPE_G :
arg == "-u" || arg == "-U" ? VizConfig::TYPE_U :
arg == "-x" || arg == "-X" ? VizConfig::TYPE_X : VizConfig::TYPE_S;
config.groups.push_back({type, design->selection_stack.back()});
design->selection_stack.pop_back();
config.groups.push_back({type, design->selection()});
design->pop_selection();
continue;
}
if (arg == "-0" || arg == "-1" || arg == "-2" || arg == "-3" || arg == "-4" ||

2
passes/hierarchy/submod.cc
View file

@ -246,7 +246,7 @@ struct SubmodWorker
SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
{
if (!design->selected_whole_module(module->name) && opt_name.empty())
if (!module->is_selected_whole() && opt_name.empty())
return;
if (module->processes.size() > 0) {

2
passes/sat/cutpoint.cc
View file

@ -57,7 +57,7 @@ struct CutpointPass : public Pass {
for (auto module : design->selected_modules())
{
if (design->selected_whole_module(module->name)) {
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))

4
passes/techmap/abc9.cc
View file

@ -400,7 +400,7 @@ struct Abc9Pass : public ScriptPass
}
log_push();
active_design->selection().select(mod);
active_design->select(mod);
if (!active_design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod));
@ -452,7 +452,7 @@ struct Abc9Pass : public ScriptPass
log_pop();
}
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}

2
passes/techmap/abc9_ops.cc
View file

@ -454,7 +454,7 @@ void prep_bypass(RTLIL::Design *design)
void prep_dff(RTLIL::Design *design)
{
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false, false, design)));
auto &modules_sel = r.first->second;
for (auto module : design->selected_modules())

4
passes/techmap/abc_new.cc
View file

@ -157,7 +157,7 @@ struct AbcNewPass : public ScriptPass {
exe_options = abc_exe_options;
log_header(active_design, "Mapping module '%s'.\n", log_id(mod));
log_push();
active_design->selection().select(mod);
active_design->select(mod);
}
std::string script_save;
@ -194,7 +194,7 @@ struct AbcNewPass : public ScriptPass {
}
if (!help_mode) {
active_design->selection_stack.pop_back();
active_design->pop_selection();
}
}
}

2
passes/techmap/aigmap.cc
View file

@ -172,7 +172,7 @@ struct AigmapPass : public Pass {
if (select_mode) {
log_assert(!design->selection_stack.empty());
RTLIL::Selection& sel = design->selection_stack.back();
RTLIL::Selection& sel = design->selection();
sel.selected_members[module->name] = std::move(new_sel);
}

2
passes/techmap/nlutmap.cc
View file

@ -42,7 +42,7 @@ struct NlutmapWorker
RTLIL::Selection get_selection()
{
RTLIL::Selection sel(false);
RTLIL::Selection sel(false, false, module->design);
for (auto cell : module->cells())
if (!mapped_cells.count(cell))
sel.select(module, cell);