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https://github.com/YosysHQ/yosys
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Use selection helpers
Catch more uses of selection constructor without assigning a design.
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parent
a67b57bd64
commit
dac2bb7d4d
23 changed files with 84 additions and 78 deletions
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@ -318,18 +318,18 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
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pass_register[args[0]]->execute(args, design);
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pass_register[args[0]]->post_execute(state);
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while (design->selection_stack.size() > orig_sel_stack_pos)
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design->selection_stack.pop_back();
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design->pop_selection();
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}
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void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module.clear();
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design->selection_stack.push_back(selection);
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design->push_selection(selection);
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Pass::call(design, command);
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design->selection_stack.pop_back();
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design->pop_selection();
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design->selected_active_module = backup_selected_active_module;
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}
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@ -337,11 +337,11 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module.clear();
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design->selection_stack.push_back(selection);
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design->push_selection(selection);
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Pass::call(design, args);
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design->selection_stack.pop_back();
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design->pop_selection();
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design->selected_active_module = backup_selected_active_module;
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}
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@ -349,12 +349,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->name.str();
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design->selection_stack.push_back(RTLIL::Selection(false));
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design->selection_stack.back().select(module);
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design->push_empty_selection();
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design->select(module);
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Pass::call(design, command);
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design->selection_stack.pop_back();
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design->pop_selection();
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design->selected_active_module = backup_selected_active_module;
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}
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@ -362,12 +362,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vec
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->name.str();
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design->selection_stack.push_back(RTLIL::Selection(false));
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design->selection_stack.back().select(module);
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design->push_empty_selection();
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design->select(module);
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Pass::call(design, args);
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design->selection_stack.pop_back();
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design->pop_selection();
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design->selected_active_module = backup_selected_active_module;
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}
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@ -745,7 +745,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
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}
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while (design->selection_stack.size() > orig_sel_stack_pos)
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design->selection_stack.pop_back();
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design->pop_selection();
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}
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struct SimHelper {
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