mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Added GP_VREF cell

Browse source
This commit is contained in:
Andrew Zonenberg 2016-04-20 20:48:19 -07:00
parent bf64974d43
commit d90c1e9522
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/greenpak4/cells_sim.v
View file

@ -263,6 +263,12 @@ module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP_VREF(input VIN, output reg VOUT);
parameter VIN_DIV = 1;
parameter VREF = 0;
//cannot simulate mixed signal IP
endmodule
module GP_VSS(output OUT);
assign OUT = 0;
endmodule