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Convert todo comments to directives

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Could be left in for final version, but my current thinking is not?
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Krystine Sherwin 2023-08-08 10:04:07 +12:00
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12
docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -639,13 +639,15 @@ to extend the actual Verilog frontend.
Synthesizing Verilog arrays
---------------------------
.. TODO: these
.. todo::
Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
how they are processed in the memory pass.
Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
how they are processed in the memory pass.
Synthesizing parametric designs
-------------------------------
Add some information on the ``RTLIL::Module::derive()`` method and how it is
used to synthesize parametric modules via the hierarchy pass.
.. todo::
Add some information on the ``RTLIL::Module::derive()`` method and how it is
used to synthesize parametric modules via the hierarchy pass.