diff --git a/docs/source/conf.py b/docs/source/conf.py index bca4971e9..fb2e603f1 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -59,6 +59,10 @@ latex_elements = { ''' } +# include todos during rewrite +extensions.append('sphinx.ext.todo') +todo_include_todos = True + def setup(sphinx): sys.path += [os.path.dirname(__file__) + "/../util"] from RtlilLexer import RtlilLexer diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index 9f7ae2ba7..10894e4e8 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -1,7 +1,7 @@ Scripting in Yosys ------------------ -.. TODO: copypaste +.. todo:: copypaste Yosys reads and processes commands from synthesis scripts, command line arguments and an interactive command prompt. Yosys commands consist of a command diff --git a/docs/source/getting_started/typical_phases.rst b/docs/source/getting_started/typical_phases.rst index 45921aa75..7f4f0880b 100644 --- a/docs/source/getting_started/typical_phases.rst +++ b/docs/source/getting_started/typical_phases.rst @@ -1,7 +1,7 @@ Typical phases of a synthesis flow ---------------------------------- -.. TODO: copypaste +.. todo:: copypaste - Reading and elaborating the design - Higher-level synthesis and optimization diff --git a/docs/source/index.rst b/docs/source/index.rst index 0cae4aa0d..df335444d 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -12,3 +12,8 @@ Yosys Open SYnthesis Suite test_suites appendix + +TODOs +----- + +.. todolist:: diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst index 81d89d7a6..8c9450feb 100644 --- a/docs/source/introduction.rst +++ b/docs/source/introduction.rst @@ -1,7 +1,7 @@ What is Yosys ============= -.. TODO: rewrite to not be a thesis abstract +.. todo:: rewrite to not be a thesis abstract :Abstract: Most of today's digital design is done in HDL code (mostly Verilog or @@ -125,7 +125,7 @@ In no particular order: History of Yosys ---------------- -.. TODO: copypaste +.. todo:: copypaste A Hardware Description Language (HDL) is a computer language used to describe circuits. A HDL synthesis tool is a computer program that takes a formal diff --git a/docs/source/test_suites.rst b/docs/source/test_suites.rst index bc56bbf77..7f23754b2 100644 --- a/docs/source/test_suites.rst +++ b/docs/source/test_suites.rst @@ -4,7 +4,7 @@ Test suites .. note:: Potentially significantly out of date information last updated circa 2015 -.. TODO: copypaste +.. todo:: copypaste Continuously checking the correctness of Yosys and making sure that new features do not break old ones is a high priority in Yosys. Two external test suites diff --git a/docs/source/using_yosys/more_scripting/opt_passes.rst b/docs/source/using_yosys/more_scripting/opt_passes.rst index 387a3fb1f..06eafe4e9 100644 --- a/docs/source/using_yosys/more_scripting/opt_passes.rst +++ b/docs/source/using_yosys/more_scripting/opt_passes.rst @@ -3,7 +3,7 @@ Optimization passes =================== -.. TODO: copypaste +.. todo:: copypaste Yosys employs a number of optimizations to generate better and cleaner results. This chapter outlines these optimizations. diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index 5e5bf8ae4..528989877 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -1,8 +1,7 @@ Selections ---------- -.. TODO: copypaste - +.. todo:: copypaste Most Yosys commands make use of the "selection framework" of Yosys. It can be used to apply commands only to part of the design. For example: diff --git a/docs/source/yosys_internals/extensions.rst b/docs/source/yosys_internals/extensions.rst index 1b601acbd..225aa23eb 100644 --- a/docs/source/yosys_internals/extensions.rst +++ b/docs/source/yosys_internals/extensions.rst @@ -3,7 +3,7 @@ Writing extensions ================== -.. TODO: copypaste +.. todo:: copypaste This chapter contains some bits and pieces of information about programming yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack. @@ -81,7 +81,7 @@ look at the output of ``dump`` and ``show`` before and after the command has been executed can be helpful. The :doc:`/using_yosys/more_scripting/selections` document has more information on using these commands. -.. TODO: copypaste +.. todo:: copypaste Creating modules from scratch ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/yosys_internals/flow/command_ordering.rst b/docs/source/yosys_internals/flow/command_ordering.rst index 1724ba5e3..8419ea4a2 100644 --- a/docs/source/yosys_internals/flow/command_ordering.rst +++ b/docs/source/yosys_internals/flow/command_ordering.rst @@ -1,7 +1,7 @@ Command ordering ---------------- -.. TODO: copypaste +.. todo:: copypaste Intro to coarse-grain synthesis ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -36,7 +36,7 @@ The extract pass with an instance of the module from the map file. - In a way the ``extract`` pass is the inverse of the techmap pass. -.. TODO: copypaste +.. todo:: copypaste .. figure:: ../../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.* :class: width-helper @@ -118,7 +118,7 @@ Preconditioning: ``macc_xilinx_swap_map.v`` Make sure ``A`` is the smaller port on all multipliers -.. TODO: copypaste +.. todo:: copypaste .. literalinclude:: ../../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v :language: verilog diff --git a/docs/source/yosys_internals/flow/control_and_data.rst b/docs/source/yosys_internals/flow/control_and_data.rst index 65eaaa5d5..961687f79 100644 --- a/docs/source/yosys_internals/flow/control_and_data.rst +++ b/docs/source/yosys_internals/flow/control_and_data.rst @@ -1,7 +1,7 @@ Control and data flow ===================== -.. TODO: copypaste +.. todo:: copypaste The data- and control-flow of a typical synthesis tool is very similar to the data- and control-flow of a typical compiler: different subsystems are called in diff --git a/docs/source/yosys_internals/flow/model_checking.rst b/docs/source/yosys_internals/flow/model_checking.rst index 3ac73fd6f..c023109c9 100644 --- a/docs/source/yosys_internals/flow/model_checking.rst +++ b/docs/source/yosys_internals/flow/model_checking.rst @@ -1,7 +1,7 @@ Symbolic model checking ----------------------- -.. TODO: copypaste +.. todo:: copypaste .. note:: diff --git a/docs/source/yosys_internals/flow/overview.rst b/docs/source/yosys_internals/flow/overview.rst index 025d6f8b7..acb7dbaab 100644 --- a/docs/source/yosys_internals/flow/overview.rst +++ b/docs/source/yosys_internals/flow/overview.rst @@ -1,7 +1,7 @@ Flow overview ============= -.. TODO: copypaste +.. todo:: copypaste :numref:`Figure %s ` shows the simplified data flow within Yosys. Rectangles in the figure represent program modules and ellipses internal diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index cb5b65d8a..fcfda6746 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -639,13 +639,15 @@ to extend the actual Verilog frontend. Synthesizing Verilog arrays --------------------------- -.. TODO: these +.. todo:: -Add some information on the generation of ``$memrd`` and ``$memwr`` cells and -how they are processed in the memory pass. + Add some information on the generation of ``$memrd`` and ``$memwr`` cells and + how they are processed in the memory pass. Synthesizing parametric designs ------------------------------- -Add some information on the ``RTLIL::Module::derive()`` method and how it is -used to synthesize parametric modules via the hierarchy pass. +.. todo:: + + Add some information on the ``RTLIL::Module::derive()`` method and how it is + used to synthesize parametric modules via the hierarchy pass. diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst index 7768c3cc9..8fa9e94dc 100644 --- a/docs/source/yosys_internals/formats/cell_library.rst +++ b/docs/source/yosys_internals/formats/cell_library.rst @@ -1,7 +1,7 @@ .. role:: verilog(code) :language: Verilog -.. TODO: copypaste +.. todo:: copypaste .. _chapter:celllib: diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index 4ed7d9107..a65fedc30 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -74,7 +74,7 @@ This has three advantages: - First, it is impossible that an auto-generated identifier collides with an identifier that was provided by the user. -.. TODO: does opt_rmunused (still?) exist? +.. todo:: does opt_rmunused (still?) exist? - Second, the information about which identifiers were originally provided by the user is always available which can help guide some optimizations. For diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst index e8d6fd1a0..c8b55cb8d 100644 --- a/docs/source/yosys_internals/index.rst +++ b/docs/source/yosys_internals/index.rst @@ -3,7 +3,7 @@ Yosys internals =============== -.. TODO: copypaste +.. todo:: copypaste Yosys is an extensible open source hardware synthesis tool. It is aimed at designers who are looking for an easily accessible, universal, and @@ -38,4 +38,4 @@ can be used as reference to implement a similar system in any language. techmap extensions -.. TODO: copypaste +.. todo:: copypaste diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst index 745e5e2f5..a095ef6bf 100644 --- a/docs/source/yosys_internals/techmap.rst +++ b/docs/source/yosys_internals/techmap.rst @@ -1,6 +1,6 @@ .. _chapter:techmap: -.. TODO: copypaste +.. todo:: copypaste Technology mapping ================== @@ -109,7 +109,7 @@ sensitive information from the Liberty file. Techmap by example ------------------ -.. TODO: copypaste +.. todo:: copypaste As a quick recap, the ``techmap`` command replaces cells in the design with implementations given as Verilog code (called "map files"). It can replace