Convert todo comments to directives

Could be left in for final version, but my current thinking is not?

docs/source/yosys_internals/flow/command_ordering.rst

@@ -1,7 +1,7 @@
 Command ordering
 ----------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 Intro to coarse-grain synthesis
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -36,7 +36,7 @@ The extract pass
   with an instance of the module from the map file.
 - In a way the ``extract`` pass is the inverse of the techmap pass.
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. figure:: ../../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
     :class: width-helper
@@ -118,7 +118,7 @@ Preconditioning: ``macc_xilinx_swap_map.v``
 
 Make sure ``A`` is the smaller port on all multipliers
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. literalinclude:: ../../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
    :language: verilog

docs/source/yosys_internals/flow/control_and_data.rst

@@ -1,7 +1,7 @@
 Control and data flow
 =====================
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 The data- and control-flow of a typical synthesis tool is very similar to the
 data- and control-flow of a typical compiler: different subsystems are called in

docs/source/yosys_internals/flow/model_checking.rst

@@ -1,7 +1,7 @@
 Symbolic model checking
 -----------------------
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 .. note:: 
     

docs/source/yosys_internals/flow/overview.rst

@@ -1,7 +1,7 @@
 Flow overview
 =============
 
-.. TODO: copypaste
+.. todo:: copypaste
 
 :numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
 Yosys. Rectangles in the figure represent program modules and ellipses internal

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -639,13 +639,15 @@ to extend the actual Verilog frontend.
 Synthesizing Verilog arrays
 ---------------------------
 
-.. TODO: these
+.. todo:: 
 
-Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
-how they are processed in the memory pass.
+  Add some information on the generation of ``$memrd`` and ``$memwr`` cells and
+  how they are processed in the memory pass.
 
 Synthesizing parametric designs
 -------------------------------
 
-Add some information on the ``RTLIL::Module::derive()`` method and how it is
-used to synthesize parametric modules via the hierarchy pass.
+.. todo::
+
+  Add some information on the ``RTLIL::Module::derive()`` method and how it is
+  used to synthesize parametric modules via the hierarchy pass.