diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index c9d2f6760..637cc9be3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -891,6 +891,14 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 	}
 }
 
+void RTLIL::Selection::clear()
+{
+	full_selection = false;
+	complete_selection = false;
+	selected_modules.clear();
+	selected_members.clear();
+}
+
 RTLIL::Design::Design()
   : verilog_defines (new define_map_t)
 {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 97160e1d9..52e7a17e7 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1241,6 +1241,9 @@ struct RTLIL::Selection
 		return !selects_all() && selected_modules.empty() && selected_members.empty();
 	}
 
+	// clear this selection, leaving it empty
+	void clear();
+
 	// create a new selection which is empty
 	static Selection EmptySelection(RTLIL::Design *design = nullptr) { return Selection(false, false, design); };
 
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index c34cf43c6..1d75091af 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -159,10 +159,7 @@ static void select_all(RTLIL::Design *design, RTLIL::Selection &lhs)
 static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 {
 	if (lhs.selects_all()) {
-		lhs.full_selection = false;
-		lhs.complete_selection = false;
-		lhs.selected_modules.clear();
-		lhs.selected_members.clear();
+		lhs.clear();
 		return;
 	}
 
@@ -341,9 +338,8 @@ static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const
 			for (auto mod : new_rhs.selected_modules)
 				lhs.selected_modules.insert(mod);
 		} else {
+			lhs.clear();
 			lhs.full_selection = true;
-			lhs.selected_modules.clear();
-			lhs.selected_members.clear();
 		}
 		return;
 	}
@@ -361,10 +357,7 @@ static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const
 static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
 {
 	if (rhs.complete_selection) {
-		lhs.full_selection = false;
-		lhs.complete_selection = false;
-		lhs.selected_modules.clear();
-		lhs.selected_members.clear();
+		lhs.clear();
 		return;
 	}
 
@@ -378,9 +371,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
 				lhs.selected_members.erase(mod);
 			}
 		} else {
-			lhs.full_selection = false;
-			lhs.selected_modules.clear();
-			lhs.selected_members.clear();
+			lhs.clear();
 		}
 		return;
 	}
@@ -435,10 +426,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 		return;
 
 	if (rhs.empty()) {
-		lhs.full_selection = false;
-		lhs.complete_selection = false;
-		lhs.selected_modules.clear();
-		lhs.selected_members.clear();
+		lhs.clear();
 		return;
 	}
 
@@ -680,9 +668,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
 		return;
 
 	if (sel.full_selection) {
-		sel.full_selection = false;
-		sel.selected_modules.clear();
-		sel.selected_members.clear();
+		sel.clear();
 		sel.selected_modules.insert(design->selected_active_module);
 		return;
 	}