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	Merge pull request #4931 from povik/buf-clean
opt_clean, simplemap: Add `$buf` handling
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						d8a4991289
					
				
					 4 changed files with 24 additions and 2 deletions
				
			
		|  | @ -601,7 +601,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool | ||||||
| 
 | 
 | ||||||
| 	std::vector<RTLIL::Cell*> delcells; | 	std::vector<RTLIL::Cell*> delcells; | ||||||
| 	for (auto cell : module->cells()) | 	for (auto cell : module->cells()) | ||||||
| 		if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) { | 		if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) { | ||||||
| 			bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool(); | 			bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool(); | ||||||
| 			RTLIL::SigSpec a = cell->getPort(ID::A); | 			RTLIL::SigSpec a = cell->getPort(ID::A); | ||||||
| 			RTLIL::SigSpec y = cell->getPort(ID::Y); | 			RTLIL::SigSpec y = cell->getPort(ID::Y); | ||||||
|  |  | ||||||
|  | @ -42,6 +42,14 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) | ||||||
| 	} | 	} | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
|  | void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell) | ||||||
|  | { | ||||||
|  | 	RTLIL::SigSpec sig_a = cell->getPort(ID::A); | ||||||
|  | 	RTLIL::SigSpec sig_y = cell->getPort(ID::Y); | ||||||
|  | 
 | ||||||
|  | 	module->connect(RTLIL::SigSig(sig_y, sig_a)); | ||||||
|  | } | ||||||
|  | 
 | ||||||
| void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) | void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell) | ||||||
| { | { | ||||||
| 	RTLIL::SigSpec sig_a = cell->getPort(ID::A); | 	RTLIL::SigSpec sig_a = cell->getPort(ID::A); | ||||||
|  | @ -411,6 +419,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> | ||||||
| { | { | ||||||
| 	mappers[ID($not)]         = simplemap_not; | 	mappers[ID($not)]         = simplemap_not; | ||||||
| 	mappers[ID($pos)]         = simplemap_pos; | 	mappers[ID($pos)]         = simplemap_pos; | ||||||
|  | 	mappers[ID($buf)]         = simplemap_buf; | ||||||
| 	mappers[ID($and)]         = simplemap_bitop; | 	mappers[ID($and)]         = simplemap_bitop; | ||||||
| 	mappers[ID($or)]          = simplemap_bitop; | 	mappers[ID($or)]          = simplemap_bitop; | ||||||
| 	mappers[ID($xor)]         = simplemap_bitop; | 	mappers[ID($xor)]         = simplemap_bitop; | ||||||
|  |  | ||||||
|  | @ -59,7 +59,7 @@ module _90_simplemap_compare_ops; | ||||||
| endmodule | endmodule | ||||||
| 
 | 
 | ||||||
| (* techmap_simplemap *) | (* techmap_simplemap *) | ||||||
| (* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) | (* techmap_celltype = "$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *) | ||||||
| module _90_simplemap_various; | module _90_simplemap_various; | ||||||
| endmodule | endmodule | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
							
								
								
									
										13
									
								
								tests/techmap/buf.ys
									
										
									
									
									
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								tests/techmap/buf.ys
									
										
									
									
									
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							|  | @ -0,0 +1,13 @@ | ||||||
|  | read_verilog -icells <<EOF | ||||||
|  | module top(input wire [2:0] a, output wire [2:0] y); | ||||||
|  | 	\$buf #(.WIDTH(3)) b(.A(a), .Y(y)); | ||||||
|  | endmodule | ||||||
|  | EOF | ||||||
|  | design -save save | ||||||
|  | 
 | ||||||
|  | opt_clean | ||||||
|  | select -assert-none t:$buf | ||||||
|  | 
 | ||||||
|  | design -load save | ||||||
|  | techmap | ||||||
|  | select -assert-none t:$buf | ||||||
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