From 557047fe1eda02d1c0bc34478a7bbfb4cebc1fc4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Fri, 7 Mar 2025 12:07:02 +0100
Subject: [PATCH] opt_clean, simplemap: Add `$buf` handling

---
 passes/opt/opt_clean.cc     |  2 +-
 passes/techmap/simplemap.cc |  9 +++++++++
 techlibs/common/techmap.v   |  2 +-
 tests/techmap/buf.ys        | 13 +++++++++++++
 4 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 tests/techmap/buf.ys

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 51212fa0e..c37c03607 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -601,7 +601,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
 
 	std::vector<RTLIL::Cell*> delcells;
 	for (auto cell : module->cells())
-		if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
+		if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
 			bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
 			RTLIL::SigSpec a = cell->getPort(ID::A);
 			RTLIL::SigSpec y = cell->getPort(ID::Y);
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 7461460fe..b23985770 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -42,6 +42,14 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
+void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	RTLIL::SigSpec sig_a = cell->getPort(ID::A);
+	RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
+
+	module->connect(RTLIL::SigSig(sig_y, sig_a));
+}
+
 void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	RTLIL::SigSpec sig_a = cell->getPort(ID::A);
@@ -411,6 +419,7 @@ void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)>
 {
 	mappers[ID($not)]         = simplemap_not;
 	mappers[ID($pos)]         = simplemap_pos;
+	mappers[ID($buf)]         = simplemap_buf;
 	mappers[ID($and)]         = simplemap_bitop;
 	mappers[ID($or)]          = simplemap_bitop;
 	mappers[ID($xor)]         = simplemap_bitop;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 119296147..6cf4f3415 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_compare_ops;
 endmodule
 
 (* techmap_simplemap *)
-(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *)
+(* techmap_celltype = "$buf $pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *)
 module _90_simplemap_various;
 endmodule
 
diff --git a/tests/techmap/buf.ys b/tests/techmap/buf.ys
new file mode 100644
index 000000000..2b2534fab
--- /dev/null
+++ b/tests/techmap/buf.ys
@@ -0,0 +1,13 @@
+read_verilog -icells <<EOF
+module top(input wire [2:0] a, output wire [2:0] y);
+	\$buf #(.WIDTH(3)) b(.A(a), .Y(y));
+endmodule
+EOF
+design -save save
+
+opt_clean
+select -assert-none t:$buf
+
+design -load save
+techmap
+select -assert-none t:$buf