mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-04 21:33:35 +00:00
Code Activity

Fix typo in comment about address collision pattern

Browse source
This commit is contained in:
Janeczko Jakub 2026-08-03 19:27:58 +02:00 • committed by nella
parent 0b0f5cbf26
commit d840a852a9
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/verilog/verilog_backend.cc
View file

@ -602,8 +602,8 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
}
}
// Due to some synthesis tools being incompetent in detecting address colission pattern
// from verilog with strictly defined semantics and not infering bram (see github issue #5082),
// Due to some synthesis tools being incompetent in detecting address collision pattern
// from verilog with strictly defined semantics and not inferring bram (see github issue #5082),
// memory cannot use:
// 1. e.g Vivado assumes non-transparent port
// assign r_data = mem[latched r_addr];