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anlogic: add support for Eagle Distributed RAM

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The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
This commit is contained in:
Icenowy Zheng 2018-12-14 16:50:37 +08:00
parent 634d7d1c14
commit d53a2bd1d3
4 changed files with 43 additions and 1 deletions
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19
techlibs/anlogic/drams_map.v Normal file
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@ -0,0 +1,19 @@
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input CLK1;
input [3:0] A1ADDR;
output [3:0] A1DATA;
input [3:0] B1ADDR;
input [3:0] B1DATA;
input B1EN;
EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
.di(B1DATA),
.waddr(B1ADDR),
.wclk(CLK1),
.we(B1EN),
.raddr(A1ADDR),
.do(A1DATA)
);
endmodule