mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-25 10:51:30 +00:00
Code Activity

Update passes/memory to avoid bits()

Browse source
This commit is contained in:
Robert O'Callahan 2025-08-28 03:53:14 +00:00
parent 7c3cf9cc42
commit d4e2fa0c4f
2 changed files with 9 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

7
passes/memory/memory_share.cc
View file

@ -60,16 +60,17 @@ struct MemoryShareWorker
bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) {
res = Const(State::Sx, mem.width << wide_log2);
for (int i = 0; i < GetSize(src1); i++)
res.bits()[i + sub1 * mem.width] = src1[i];
res.set(i + sub1 * mem.width, src1[i]);
for (int i = 0; i < GetSize(src2); i++) {
if (src2[i] == State::Sx)
continue;
auto &dst = res.bits()[i + sub2 * mem.width];
int idx = i + sub2 * mem.width;
RTLIL::State dst = res[idx];
if (dst == src2[i])
continue;
if (dst != State::Sx)
return false;
dst = src2[i];
res.set(idx, src2[i]);
}
return true;
}