diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 9db329c5c..e819a14c5 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -848,9 +848,9 @@ grow_read_ports:; for (int i = 0; i < mem.width; i++) if (shuffle_map[i] != -1) { module->connect(port.data[shuffle_map[i]], new_data[i]); - new_init_value.bits()[i] = port.init_value[shuffle_map[i]]; - new_arst_value.bits()[i] = port.arst_value[shuffle_map[i]]; - new_srst_value.bits()[i] = port.srst_value[shuffle_map[i]]; + new_init_value.set(i, port.init_value[shuffle_map[i]]); + new_arst_value.set(i, port.arst_value[shuffle_map[i]]); + new_srst_value.set(i, port.srst_value[shuffle_map[i]]); } port.data = new_data; port.init_value = new_init_value; @@ -887,9 +887,9 @@ grow_read_ports:; for (int i = 0; i < init_size; i++) for (int j = 0; j < bram.dbits; j++) if (init_offset+i < GetSize(initdata) && init_offset+i >= 0) - initparam.bits()[i*bram.dbits+j] = initdata[init_offset+i][init_shift+j]; + initparam.set(i*bram.dbits+j, initdata[init_offset+i][init_shift+j]); else - initparam.bits()[i*bram.dbits+j] = State::Sx; + initparam.set(i*bram.dbits+j, State::Sx); c->setParam(ID::INIT, initparam); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index a19807f22..62ab09059 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -60,16 +60,17 @@ struct MemoryShareWorker bool merge_rst_value(Mem &mem, Const &res, int wide_log2, const Const &src1, int sub1, const Const &src2, int sub2) { res = Const(State::Sx, mem.width << wide_log2); for (int i = 0; i < GetSize(src1); i++) - res.bits()[i + sub1 * mem.width] = src1[i]; + res.set(i + sub1 * mem.width, src1[i]); for (int i = 0; i < GetSize(src2); i++) { if (src2[i] == State::Sx) continue; - auto &dst = res.bits()[i + sub2 * mem.width]; + int idx = i + sub2 * mem.width; + RTLIL::State dst = res[idx]; if (dst == src2[i]) continue; if (dst != State::Sx) return false; - dst = src2[i]; + res.set(idx, src2[i]); } return true; }