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use more standard naming conventions

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Rahul Bhagwat 2025-08-06 15:39:30 -04:00
parent 7e0157ba2b
commit d3c8e6c14c
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2 changed files with 16 additions and 15 deletions
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9
tests/verilog/package_import_separate.sv
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@ -1,13 +1,14 @@
package config_pkg; package package_import_separate;
localparam integer localparam integer
DATA_WIDTH = 8, DATAWIDTH = 8,
ADDR_WIDTH = 4; ADDRWIDTH = 4;
localparam logic [2:0] localparam logic [2:0]
IDLE = 3'b000, IDLE = 3'b000,
START = 3'b001, START = 3'b001,
DATA = 3'b010, DATA = 3'b010,
ODD_PARITY = 3'b011,
STOP = 3'b100, STOP = 3'b100,
DONE = 3'b101; DONE = 3'b101;
endpackage endpackage

10
tests/verilog/package_import_separate_module.sv
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@ -1,8 +1,8 @@
import config_pkg::*; import package_import_separate::*;
module top; module package_import_separate_module;
logic [DATA_WIDTH-1:0] data; logic [DATAWIDTH-1:0] data;
logic [ADDR_WIDTH-1:0] addr; logic [ADDRWIDTH-1:0] addr;
logic [2:0] state; logic [2:0] state;
always_comb begin always_comb begin
@ -10,10 +10,10 @@ module top;
IDLE: data = 8'h00; IDLE: data = 8'h00;
START: data = 8'h01; START: data = 8'h01;
DATA: data = 8'h02; DATA: data = 8'h02;
ODD_PARITY: data = 8'h03;
STOP: data = 8'h04; STOP: data = 8'h04;
DONE: data = 8'h05; DONE: data = 8'h05;
default: data = 8'hFF; default: data = 8'hFF;
endcase endcase
end end
endmodule endmodule