diff --git a/tests/verilog/package_import_separate.sv b/tests/verilog/package_import_separate.sv
index eddde709b..2337e4bce 100644
--- a/tests/verilog/package_import_separate.sv
+++ b/tests/verilog/package_import_separate.sv
@@ -1,13 +1,14 @@
-package config_pkg;
+package package_import_separate;
+
   localparam integer
-    DATA_WIDTH = 8,
-    ADDR_WIDTH = 4;
+    DATAWIDTH = 8,
+    ADDRWIDTH = 4;
 
   localparam logic [2:0]
-    IDLE = 3'b000,
+    IDLE  = 3'b000,
     START = 3'b001,
-    DATA = 3'b010,
-    ODD_PARITY = 3'b011,
-    STOP = 3'b100,
-    DONE = 3'b101;
+    DATA  = 3'b010,
+    STOP  = 3'b100,
+    DONE  = 3'b101;
+
 endpackage
diff --git a/tests/verilog/package_import_separate_module.sv b/tests/verilog/package_import_separate_module.sv
index f940553b3..b58d3b814 100644
--- a/tests/verilog/package_import_separate_module.sv
+++ b/tests/verilog/package_import_separate_module.sv
@@ -1,19 +1,19 @@
-import config_pkg::*;
+import package_import_separate::*;
 
-module top;
-  logic [DATA_WIDTH-1:0] data;
-  logic [ADDR_WIDTH-1:0] addr;
+module package_import_separate_module;
+  logic [DATAWIDTH-1:0] data;
+  logic [ADDRWIDTH-1:0] addr;
   logic [2:0] state;
-  
+
   always_comb begin
     case (state)
       IDLE: data = 8'h00;
       START: data = 8'h01;
       DATA: data = 8'h02;
-      ODD_PARITY: data = 8'h03;
       STOP: data = 8'h04;
       DONE: data = 8'h05;
       default: data = 8'hFF;
     endcase
   end
-endmodule 
\ No newline at end of file
+
+endmodule