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use more standard naming conventions

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Rahul Bhagwat 2025-08-06 15:39:30 -04:00
parent 7e0157ba2b
commit d3c8e6c14c
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2 changed files with 16 additions and 15 deletions
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14
tests/verilog/package_import_separate_module.sv
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@ -1,19 +1,19 @@
import config_pkg::*;
import package_import_separate::*;
module top;
logic [DATA_WIDTH-1:0] data;
logic [ADDR_WIDTH-1:0] addr;
module package_import_separate_module;
logic [DATAWIDTH-1:0] data;
logic [ADDRWIDTH-1:0] addr;
logic [2:0] state;
always_comb begin
case (state)
IDLE: data = 8'h00;
START: data = 8'h01;
DATA: data = 8'h02;
ODD_PARITY: data = 8'h03;
STOP: data = 8'h04;
DONE: data = 8'h05;
default: data = 8'hFF;
endcase
end
endmodule
endmodule