mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-27 03:41:30 +00:00
Code Activity

Update passes/cmds to avoid bits()

Browse source
This commit is contained in:
Robert O'Callahan 2025-08-28 03:52:40 +00:00
parent 24a95bd6cf
commit d318775d97
6 changed files with 26 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

7
passes/cmds/splitnets.cc
View file

@ -75,10 +75,11 @@ struct SplitnetsWorker
it = wire->attributes.find(ID::init);
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
Const old_init = it->second;
RTLIL::Const::Builder new_init_bits_builder(width);
for (int i = offset; i < offset+width; i++)
new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
new_init_bits_builder.push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init_bits_builder.build());
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();