From d318775d972061ccb4cfd9346797555235ed9753 Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Thu, 28 Aug 2025 03:52:40 +0000 Subject: [PATCH] Update passes/cmds to avoid bits() --- passes/cmds/bugpoint.cc | 6 +++++- passes/cmds/clean_zerowidth.cc | 6 +++--- passes/cmds/dft_tag.cc | 6 ++++-- passes/cmds/setundef.cc | 8 ++++---- passes/cmds/splitnets.cc | 7 ++++--- passes/cmds/xprop.cc | 12 ++++++------ 6 files changed, 26 insertions(+), 19 deletions(-) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 08dc76dda..c66f27765 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -405,7 +405,11 @@ struct BugpointPass : public Pass { for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) { auto &mask = it2->priority_mask; if (GetSize(mask) > i) { - mask.bits().erase(mask.bits().begin() + i); + RTLIL::Const::Builder new_mask_builder(GetSize(mask) - 1); + for (int k = 0; k < GetSize(mask); k++) + if (k != i) + new_mask_builder.push_back(mask[k]); + mask = new_mask_builder.build(); } } return design_copy; diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index 48a8864c0..021726450 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -158,11 +158,11 @@ struct CleanZeroWidthPass : public Pass { continue; if (GetSize(memwr.address) == 0) memwr.address = State::S0; - Const priority_mask; + RTLIL::Const::Builder new_mask_bits(swizzle.size()); for (auto x : swizzle) { - priority_mask.bits().push_back(memwr.priority_mask[x]); + new_mask_bits.push_back(memwr.priority_mask[x]); } - memwr.priority_mask = priority_mask; + memwr.priority_mask = new_mask_bits.build(); swizzle.push_back(i); new_memwr_actions.push_back(memwr); } diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 347c8efa4..c2606f50d 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -884,8 +884,10 @@ struct DftTagWorker { { if (sig_a.is_fully_const()) { auto const_val = sig_a.as_const(); - for (State& bit : const_val.bits()) - bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit; + for (auto bit : const_val) { + State b = bit; + bit = b == State::S0 ? State::S1 : b == State::S1 ? State::S0 : b; + } return const_val; } return module->Not(name, sig_a); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index dce33c05b..61c35d26e 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -243,7 +243,7 @@ struct SetundefPass : public Pass { { for (auto *cell : module->selected_cells()) { for (auto ¶meter : cell->parameters) { - for (auto &bit : parameter.second.bits()) { + for (auto bit : parameter.second) { if (bit > RTLIL::State::S1) bit = worker.next_bit(); } @@ -390,12 +390,12 @@ struct SetundefPass : public Pass { for (auto wire : initwires) { Const &initval = wire->attributes[ID::init]; - initval.bits().resize(GetSize(wire), State::Sx); + initval.resize(GetSize(wire), State::Sx); for (int i = 0; i < GetSize(wire); i++) { SigBit bit = sigmap(SigBit(wire, i)); if (initval[i] == State::Sx && ffbits.count(bit)) { - initval.bits()[i] = worker.next_bit(); + initval.set(i, worker.next_bit()); ffbits.erase(bit); } } @@ -421,7 +421,7 @@ struct SetundefPass : public Pass { continue; Const &initval = wire->attributes[ID::init]; - initval.bits().resize(GetSize(wire), State::Sx); + initval.resize(GetSize(wire), State::Sx); if (initval.is_fully_undef()) { wire->attributes.erase(ID::init); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 9e606dee1..d61a99ec0 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -75,10 +75,11 @@ struct SplitnetsWorker it = wire->attributes.find(ID::init); if (it != wire->attributes.end()) { - Const old_init = it->second, new_init; + Const old_init = it->second; + RTLIL::Const::Builder new_init_bits_builder(width); for (int i = offset; i < offset+width; i++) - new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx); - new_wire->attributes.emplace(ID::init, new_init); + new_init_bits_builder.push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx); + new_wire->attributes.emplace(ID::init, new_init_bits_builder.build()); } std::vector sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index d2d0c4d8e..62c0c0cc8 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -828,9 +828,9 @@ struct XpropWorker auto init_q_is_1 = init_q; auto init_q_is_x = init_q; - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = bit == State::S1 ? State::S1 : State::S0; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = bit == State::Sx ? State::S1 : State::S0; initvals.remove_init(sig_q); @@ -865,14 +865,14 @@ struct XpropWorker auto init_q_is_x = init_q; if (ff.is_anyinit) { - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = State::Sx; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = State::S0; } else { - for (auto &bit : init_q_is_1.bits()) + for (auto bit : init_q_is_1) bit = bit == State::S1 ? State::S1 : State::S0; - for (auto &bit : init_q_is_x.bits()) + for (auto bit : init_q_is_x) bit = bit == State::Sx ? State::S1 : State::S0; }