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Update passes/cmds to avoid bits()

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This commit is contained in:
Robert O'Callahan 2025-08-28 03:52:40 +00:00
parent 24a95bd6cf
commit d318775d97
6 changed files with 26 additions and 19 deletions
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6
passes/cmds/bugpoint.cc
View file

@ -405,7 +405,11 @@ struct BugpointPass : public Pass {
for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) {
auto &mask = it2->priority_mask;
if (GetSize(mask) > i) {
mask.bits().erase(mask.bits().begin() + i);
RTLIL::Const::Builder new_mask_builder(GetSize(mask) - 1);
for (int k = 0; k < GetSize(mask); k++)
if (k != i)
new_mask_builder.push_back(mask[k]);
mask = new_mask_builder.build();
}
}
return design_copy;

6
passes/cmds/clean_zerowidth.cc
View file

@ -158,11 +158,11 @@ struct CleanZeroWidthPass : public Pass {
continue;
if (GetSize(memwr.address) == 0)
memwr.address = State::S0;
Const priority_mask;
RTLIL::Const::Builder new_mask_bits(swizzle.size());
for (auto x : swizzle) {
priority_mask.bits().push_back(memwr.priority_mask[x]);
new_mask_bits.push_back(memwr.priority_mask[x]);
}
memwr.priority_mask = priority_mask;
memwr.priority_mask = new_mask_bits.build();
swizzle.push_back(i);
new_memwr_actions.push_back(memwr);
}

6
passes/cmds/dft_tag.cc
View file

@ -884,8 +884,10 @@ struct DftTagWorker {
{
if (sig_a.is_fully_const()) {
auto const_val = sig_a.as_const();
for (State& bit : const_val.bits())
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
for (auto bit : const_val) {
State b = bit;
bit = b == State::S0 ? State::S1 : b == State::S1 ? State::S0 : b;
}
return const_val;
}
return module->Not(name, sig_a);

8
passes/cmds/setundef.cc
View file

@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
{
for (auto *cell : module->selected_cells()) {
for (auto &parameter : cell->parameters) {
for (auto &bit : parameter.second.bits()) {
for (auto bit : parameter.second) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();
}
@ -390,12 +390,12 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes[ID::init];
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
SigBit bit = sigmap(SigBit(wire, i));
if (initval[i] == State::Sx && ffbits.count(bit)) {
initval.bits()[i] = worker.next_bit();
initval.set(i, worker.next_bit());
ffbits.erase(bit);
}
}
@ -421,7 +421,7 @@ struct SetundefPass : public Pass {
continue;
Const &initval = wire->attributes[ID::init];
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase(ID::init);

7
passes/cmds/splitnets.cc
View file

@ -75,10 +75,11 @@ struct SplitnetsWorker
it = wire->attributes.find(ID::init);
if (it != wire->attributes.end()) {
Const old_init = it->second, new_init;
Const old_init = it->second;
RTLIL::Const::Builder new_init_bits_builder(width);
for (int i = offset; i < offset+width; i++)
new_init.bits().push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init);
new_init_bits_builder.push_back(i < GetSize(old_init) ? old_init.at(i) : State::Sx);
new_wire->attributes.emplace(ID::init, new_init_bits_builder.build());
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();

12
passes/cmds/xprop.cc
View file

@ -828,9 +828,9 @@ struct XpropWorker
auto init_q_is_1 = init_q;
auto init_q_is_x = init_q;
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = bit == State::Sx ? State::S1 : State::S0;
initvals.remove_init(sig_q);
@ -865,14 +865,14 @@ struct XpropWorker
auto init_q_is_x = init_q;
if (ff.is_anyinit) {
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = State::Sx;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = State::S0;
} else {
for (auto &bit : init_q_is_1.bits())
for (auto bit : init_q_is_1)
bit = bit == State::S1 ? State::S1 : State::S0;
for (auto &bit : init_q_is_x.bits())
for (auto bit : init_q_is_x)
bit = bit == State::Sx ? State::S1 : State::S0;
}