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mirror of https://github.com/YosysHQ/yosys synced 2026-06-14 12:55:41 +00:00

rtlil: fix zero width SigSpec crash in signorm setPort unsetPort

This commit is contained in:
Emil J. Tywoniak 2026-03-09 21:20:23 +01:00
parent bdce610f3d
commit d2bc970ef9

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@ -952,7 +952,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
if (found->second.empty()) if (found->second.empty())
fanout.erase(found); fanout.erase(found);
} }
} else { } else if (GetSize(conn_it->second)) {
Wire *w = conn_it->second.as_wire(); Wire *w = conn_it->second.as_wire();
log_assert(w->driverCell_ == this); log_assert(w->driverCell_ == this);
log_assert(w->driverPort_ == portname); log_assert(w->driverPort_ == portname);
@ -1093,7 +1093,7 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
int i = 0; int i = 0;
for (auto bit : signal) for (auto bit : signal)
fanout[bit].insert(PortBit(this, portname, i++)); fanout[bit].insert(PortBit(this, portname, i++));
} else { } else if (GetSize(signal)) {
Wire *w = signal.as_wire(); Wire *w = signal.as_wire();
log_assert(w->driverCell_ == nullptr); log_assert(w->driverCell_ == nullptr);
log_assert(w->driverPort_.empty()); log_assert(w->driverPort_.empty());