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Add new tests.

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This commit is contained in:
SergeyDegtyar 2019-08-30 09:45:33 +03:00
parent eb0a5b2293
commit d144748401
10 changed files with 200 additions and 0 deletions
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22
tests/ice40/shifter.v Normal file
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module top (
out,
clk,
in
);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
always @(posedge clk)
begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= out << 1;
out[7] <= in;
`endif
end
endmodule