mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 20:17:55 +00:00
Code Activity

Add new tests.

Browse source
This commit is contained in:
SergeyDegtyar 2019-08-30 09:45:33 +03:00
parent eb0a5b2293
commit d144748401
10 changed files with 200 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

17
tests/ice40/counter.v Normal file
View file

@ -0,0 +1,17 @@
module top (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset) begin
out <= 8'b0 ;
end else
out <= out + 1;
endmodule